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# Compute Express Link

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## Posts

- [Join the CXL Ecosystem at CXL Mini DevCon 2026](https://computeexpresslink.org/blog/join-the-cxl-ecosystem-at-cxl-mini-devcon-2026-4690/) - The CXL® Consortium is excited to welcome members to CXL Mini DevCon 2026, taking place on August 3, 2026, at the Santa Clara Marriott in Santa Clara, California. As CXL adoption accelerates across AI, cloud, memory expansion, and composable infrastructure, Mini DevCon provides a unique opportunity to learn directly from the experts driving innovation across
- [CXL® Consortium Member Spotlight: Teledyne LeCroy](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-teledyne-lecroy-4680/) - By: Gordon Getty, Director of Product Management, Teledyne LeCroy Teledyne LeCroy has been an active participant in the CXL Consortium, contributing expertise in system validation, interoperability, and technology development. In this member spotlight blog, Teledyne LeCroy shares how its involvement is helping advance CXL adoption through collaboration, identifies emerging use cases for CXL technology,
- [From NVDIMM-N to CXL® Persistent Memory: Bringing Persistence to the Memory Fabric](https://computeexpresslink.org/blog/from-nvdimm-n-to-cxl-persistent-memory-bringing-persistence-to-the-memory-fabric-4635/) - By: Netlist Introduction Early server deployments proved the value of persistent memory but also exposed a key limitation: persistence was typically constrained to socket-attached form factors and platform-specific enablement. With Compute Express Link® (CXL®), persistence can move onto a standard, cache-coherent fabric, opening new design space for scalable, composable systems. Figure 1. Persistent memory
- [Chiplet Architecture for CXL solutions](https://computeexpresslink.org/blog/chiplet-architecture-for-cxl-solutions-4558/) - CXL memory expansion has long been viewed as a way to extend system memory capacity. However, recent advancements are pushing CXL far beyond simple expansion toward fundamentally new memory architectures. The first implementations of memory expansion typically have modules attached to a host CPU’s CXL bus to augment the local DRAM on the host CPU’s
- [Scale Your AI Performance with CXL: Insights from the Xcelerated Compute Show](https://computeexpresslink.org/blog/scale-your-ai-performance-with-cxl-insights-from-the-xcelerated-compute-show-4546/) - At the inaugural Xcelerated Compute Show 2026 in New York City, the industry came together to tackle one of the most pressing challenges in modern computing: efficiently scaling infrastructure for AI. As a Media & Industry Partner, the CXL Consortium was thrilled to introduce CXL – the open standard for coherent disaggregated memory. Across keynotes,
- [CXL Dynamic Capacity Device Technology Demo with Live Multi-Host System Using MXC GEN3 Silicon](https://computeexpresslink.org/blog/cxl-dynamic-capacity-device-technology-demo-with-live-multi-host-system-using-mxc-gen3-silicon-4527/) - By: Montage Technology The promise of memory disaggregation has moved from concept to reality. Montage Technology has successfully demonstrated a fully functional CXL® Dynamic Capacity Device (DCD) system using our new CXL 3.2 x8 memory expansion controller chip, showcasing how DCD technology with Multi-Head Device (MHD) support enables memory pooling and sharing across multiple
- [Scaling your AI Performance with CXL: Join us at the Xcelerated Compute Show](https://computeexpresslink.org/blog/scaling-your-ai-performance-with-cxl-join-us-at-the-xcelerated-compute-show-4431/) - The CXL Consortium is looking forward to promoting the benefits of CXL at the Xcelerated Compute Show, taking place from March 23-24, 2026, at the Marriott Marquis Times Square in NYC. The event brings together leaders from across hyperscale, neocloud, enterprise, and the wider ecosystem. As AI and data-intensive workloads reshape infrastructure requirements, traditional server
- [“Introducing the CXL 4.0 Specification” Webinar Q&A Recap](https://computeexpresslink.org/blog/introducing-the-cxl-4-0-specification-webinar-qa-recap-4386/) - In November 2025, the CXL Consortium announced the release of the CXL 4.0 specification to meet the increasing demands of emerging workloads in today’s data centers. The specification doubles bandwidth from 64GTs to 128GTs, adds support for bundled ports, and enhances memory RAS features. Recently, Debendra Das Sharma, CXL Consortium Board Chair, and Mahesh Natu,
- [Exploring CXL® Use Cases and Implementations](https://computeexpresslink.org/webinars/exploring-cxl-use-cases-and-implementations-2853/)
- [Advancing Coherent Connectivity: Highlights from the CXL Consortium at SC25](https://computeexpresslink.org/blog/advancing-coherent-connectivity-highlights-from-the-cxl-consortium-at-sc25-4351/) - As the industry continues to push the limits of performance, efficiency, and scalability, the role of open standards has never been more critical. That innovation was on display at this year’s Supercomputing 2025 (SC25), where the CXL Consortium made a major impact by officially announcing the CXL 4.0 specification, which meets the increasing demands of
- [Exploring CXL Use Cases with CXL 3.X Switches for HPC Applications](https://computeexpresslink.org/blog/exploring-cxl-use-cases-with-cxl-3-x-switches-for-hpc-applications-4331/) - By: Panmnesia In our previous blog, we outlined the benefits of CXL for AI applications. However, we believe that beyond AI infrastructure, CXL can also be effectively applied to another representative large-scale computing system: HPC. HPC primarily runs large-scale scientific simulations—from global-scale models to atomistic and molecular simulations—and is composed of many nodes interconnected
- [Overcoming the AI Memory Wall: How CXL Memory Pooling Powers the Next Leap in Scalable AI Computing](https://computeexpresslink.org/blog/overcoming-the-ai-memory-wall-how-cxl-memory-pooling-powers-the-next-leap-in-scalable-ai-computing-4267/) - By: XConn Technologies As large language models (LLMs) and generative AI workloads continue to grow in complexity, memory is quickly becoming the new bottleneck. While GPUs are unmatched in parallel compute performance, their onboard memory capacity remains limited. Modern AI workloads, especially LLM inference with heavy KV cache usage, routinely exceed 80 to 120
- [Intel Demonstrates CXL-Based Memory Pooling for Data-Intensive Server Environments at SC25](https://computeexpresslink.org/blog/intel-sc25-demo-4245/) - By: Anil Godbole, Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group Modern data centers are under constant pressure to keep pace with rapidly expanding datasets and increasingly complex workloads. Traditional, fixed memory configurations often create inefficiencies and bottlenecks that limit performance. This demonstration shows how CXL memory pooling enables systems to
- [Experience Next-Gen Server Memory Expansion: 2TB CXL® Memory Demo with SMART Modular and Dell at SC25](https://computeexpresslink.org/blog/experience-next-gen-server-memory-expansion-2tb-cxl-memory-demo-with-smart-modular-and-dell-at-sc25-4240/) - By: SMART Modular Technologies At the upcoming SC25 event, SMART Modular Technologies proudly partners with Dell Technologies to showcase a groundbreaking demonstration of server memory expansion, pushing the boundaries of composable infrastructure. The demo, located at the CXL Pavilion (Booth #817), features a high capacity 2TB CXL-attached memory configuration using SMART’s 4-DIMM CXL Add-In
- [Fueling AI and HPC Workloads with CXL at SC25](https://computeexpresslink.org/blog/fueling-ai-and-hpc-workloads-with-cxl-at-sc25-4233/) - Modern AI and HPC workloads are pushing traditional system architecture to its limits. Training Large Language Models (LLMs) and running Generative AI real-time inferences require massive memory capacity, high bandwidth, and low latency across heterogeneous compute environments. Compute Express Link® (CXL®) offers a transformative solution that enables low-latency, coherent communication across CPUs, GPUs, and memory
- [An Overview of the CXL 3.X Specification](https://computeexpresslink.org/webinars/an-overview-of-the-cxl-3-x-specification-3942/)
- [Breaking Boundaries in Memory: Highlights from AI Infra Summit and SDC 2025](https://computeexpresslink.org/blog/breaking-boundaries-in-memory-highlights-from-ai-infra-summit-and-sdc-2025-4198/) - By: Anil Godbole, CXL Consortium MWG Chair The demand for AI and data-intensive workloads is reshaping the architecture of modern datacenters. As compute, storage, and interconnect technologies converge, composability has become a central theme in the search for scalable, efficient, and interoperable infrastructure. The CXL Consortium recently participated in the AI Infra Summit and
- [Exploring CXL Use Cases with CXL 3.X Switches for AI Applications](https://computeexpresslink.org/blog/exploring-cxl-use-cases-with-cxl-3-x-switches-for-ai-applications-4166/) - By: Panmnesia CXL 3.X technology is transitioning from discussion to real-world deployment, with growing industry attention on its necessity and potential. It is particularly well-suited as a standard for building large-scale, practical computing systems, as it enables more efficient resource utilization through memory sharing and enhances scalability and flexibility by supporting multi-level switching and
- [Expanding your memory footprint with CXL at FMS 2025](https://computeexpresslink.org/blog/expanding-your-memory-footprint-with-cxl-at-fms-2025-4133/) - Next stop AI Infra Summit AI-driven HPC and next-gen data centers are driving explosive demand for memory innovation and CXL® (Compute Express Link®) is at the forefront, addressing the need to break through the memory wall. In recognition of the groundbreaking technology and its impact, the CXL 3.x specification received the “Most Innovative Memory Technology
- [Keeping Pace with CXL Specification Revisions](https://computeexpresslink.org/blog/keeping-pace-with-cxl-specification-revisions-4088/) - By: Ettore Giliberti, Senior Staff Application Engineer at SmartDV Technologies August 2025 As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major
- [“Advantages of CXL Memory Sharing for Emerging Applications” Webinar Q&A Recap](https://computeexpresslink.org/blog/advantages-of-cxl-memory-sharing-for-emerging-applications-webinar-qa-recap-4081/) - The CXL Consortium hosted a webinar exploring the benefits of CXL memory sharing and how CXL shared memory can improve performance for Big Data Analytics, AI, and more. During the webinar, CXL Consortium members Astera Labs, Micron Technology, UnfabriX, and XConn Technologies also shared how they are deploying CXL memory sharing to improve performance for
- [Meet with CXL Representatives at FMS 2025](https://computeexpresslink.org/blog/meet-with-cxl-representatives-at-fms-2025-4055/) - The CXL Consortium is excited to return to the Future of Memory and Storage (FMS) event at the Santa Clara Convention Center August 5-7, 2025. During the event, CXL representatives will attend the following events to meet with attendees and share how CXL can help expand memory: CXL Kiosk at the Open Standards Pavilion (Booth
- [CXL Consortium Member Spotlight: XCENA](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-xcena-4000/) - By: Jay Yeon, Senior Marketing Manager CXL Consortium member XCENA recently participated in a Q&A session to discuss CXL use cases and the benefits for hyperscale data centers, database companies, and High-Performance Computing industries. Can you please tell the CXL community about XCENA ? XCENA is a South Korea-based fabless startup tackling the memory
- [CXL Community Explores CXL Use Cases at DevCon 2025](https://computeexpresslink.org/blog/cxl-community-explores-cxl-use-cases-at-devcon-2025-4006/) - By: Anil Godbole, CXL Consortium MWG Co-Chair Earlier this year, the CXL community gathered at the Santa Clara Marriott for our annual CXL Developers Conference (DevCon). During the two-day conference, CXL Consortium Working Group Chairs hosted technical trainings on the CXL 3.X specification, provided Compliance Programs updates, discussed CXL memory pooling and expansion features,
- [CXL Type 2: Use Cases for Active Memory Tiering and Near Memory Accelerators](https://computeexpresslink.org/blog/cxl-type-2-use-cases-for-active-memory-tiering-and-near-memory-accelerators-3989/) - By: Divya Vijayaraghavan, Technical Leader, Altera As the CXL ecosystem evolves, multiple use cases have emerged with two prominent frontrunners – active memory tiering and near memory compute acceleration. Active memory tiering utilizes schemes to migrate hot and cold pages between local and remote memory tiers in a system. The term hot is synonymous
- [Sometimes You Just Need More Memory, and Sometimes That Memory Needs Software](https://computeexpresslink.org/blog/sometimes-you-just-need-more-memory-and-sometimes-that-memory-needs-software-3971/)
- [Advantages of CXL Memory Sharing for Emerging Applications](https://computeexpresslink.org/webinars/advantages-of-cxl-memory-sharing-for-emerging-applications-3960/)
- [CXL Consortium Member Spotlight: Lightelligence](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-lightelligence-3937/) - By: Maurice Steinman, SVP Product Strategy and GM US, Lightelligence The CXL Consortium, supported by leading industry players, is continuing to evolve CXL technology to support compute and memory intensive workloads for business-critical applications. Consortium member Lightelligence recently participated in a Q&A session to discuss the advantages of becoming a CXL Consortium member and
- [Making Memories at HyperScale with CXL®](https://computeexpresslink.org/webinars/making-memories-at-hyperscale-with-cxl-3102/) - Presenters: Brian Morris, Google, and Prakash Chauhan, Meta CXL® (Compute Express Link®) enables the addition of a new tier of memory to the memory hierarchy using type-3 devices. There are many first-generation CXL memory expansion devices in the market that will allow this capability. However, due to additional controller and board costs and associated power
- [Montage Technology to Demonstrate Memory and Bandwidth Scaling at DevCon 2025](https://computeexpresslink.org/blog/montage-technology-to-demonstrate-memory-and-bandwidth-scaling-at-devcon-2025-3907/) - By: Geof Findley (Montage Technology) CXL®, an open, coherent, interconnect standard that enables heterogeneous computing, increases memory capacity and bandwidth, and delivers lower latencies, allows for both shared and pooled memory to support the increasing demand for higher capacity and performance in cloud computing and data centers. Building on CXL technology, Montage Technology is excited
- [Optimizing CXL implementations with Protocol Analyzers](https://computeexpresslink.org/blog/optimizing-cxl-implementations-with-protocol-analyzers-3896/) - By: Yamini Shastry (VIAVI Solutions) The growing demand for modern workloads, particularly in Artificial Intelligence (AI), Machine Learning (ML) and High-performance computing (HPC), has pushed the boundaries of traditional interconnect technologies. Compute Express Link® (CXL®) has emerged to meet these demands, offering high-speed, low-latency communication between processors, accelerators and memory devices. However, for CXL to
- [Teledyne LeCroy to Demonstrate Protocol Analyzer and Protocol Exerciser for CXL 3.X at DevCon 2025](https://computeexpresslink.org/blog/teledyne-lecroy-to-demonstrate-protocol-analyzer-and-protocol-exerciser-for-cxl-3-x-at-devcon-2025-3829/) - CXL Consortium members are actively developing a range of products and devices that include CXL memory solutions, IP, fabric implementation, switches, and software solutions, among others. Compliance and interoperability between products are essential for seamless deployment within commercial systems. CXL DevCon provides our members a unique opportunity to discuss ongoing specification developments, view solutions in
- [Boosting AI Performance with CXL](https://computeexpresslink.org/blog/boosting-ai-performance-with-cxl-3818/) - Written by: Vanessa Do, Senior Product Marketing Manager at Cadence Design Systems As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions - or even trillions - of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training.
- [Discover the Latest in CXL Innovations at DevCon 2025](https://computeexpresslink.org/blog/discover-the-latest-in-cxl-innovations-at-devcon-2025-3718/) - The CXL Consortium held the first-ever Developers Conference last year, sharing the history of CXL and exploring the industry trends that continue to drive the evolution of our technical specification. The event also provided a unique opportunity for our members to learn directly from CXL technology experts. This year’s event – taking place Tuesday, April
- [CXL 2.0 Visibility Challenges: Analyzing Exchange Performance](https://computeexpresslink.org/blog/cxl-2-0-visibility-challenges-analyzing-exchange-performance-3657/)
- [“An Overview of the CXL 3.X Specification” Webinar Q&A Recap](https://computeexpresslink.org/blog/an-overview-of-the-cxl-3-x-specification-webinar-qa-recap-3624/) - During the latest CXL Consortium webinar, Mahesh Natu (Intel Corporation) presented an overview of the CXL 3.X specification and how it provides support for AI and ML workloads for cloud and on-premise applications. Attendees also learned how CXL 3.2 builds upon these advancements for CXL memory devices, optimizing device management, functionality, and security. Watch On-Demand
- [Developing a Robust CXL Compliance Program](https://computeexpresslink.org/blog/developing-a-robust-cxl-compliance-program-3614/) - By: Michael Hall (AMD) and Nathan White (Intel), Compliance Working Group (CWG) Co-Chair Compliance and interoperability are core tenets of the CXL Consortium’s commitment to creating a successful technology standard capable of deploying in a variety of commercially available multi-vendor systems. Compliance Programs offer developers the opportunity to ensure interoperability across the industry by
- [“Breaking Memory Barriers: CXL's Game-Changing Impact on AI/ML” Webinar Q&A Recap](https://computeexpresslink.org/blog/breaking-memory-barriers-cxls-game-changing-impact-on-ai-ml-webinar-qa-recap-3554/) - During the latest CXL Consortium webinar, Steve Scargall (MemVerge) presented how CXL technology is revolutionizing data center memory performance and efficiency, highlighting the latest advancements in hardware and software. The webinar also explored how CXL is enhancing AI/ML workloads, including Retrieval-Augmented Generation (RAG), vector databases, stable diffusion, Large Language Models (LLMs) and more. Watch On-Demand
- [“Making Memories at HyperScale with CXL®” Webinar Q&A Recap](https://computeexpresslink.org/blog/making-memories-at-hyperscale-with-cxl-webinar-qa-recap-3236/) - The CXL® Consortium recently hosted a webinar exploring how CXL type-3 devices can support a new tier of memory, allowing for the expansion of platform memory capacity incrementally and cost-effectively to enable AI & HPC workloads. During the webinar, Brian Morris, Google, and Prakash Chauhan, Meta, shared an overview of the applications and use cases
- [Micron Demonstrates Memory Sharing Across a CXL Fabric at Supercomputing 2024 (SC24)](https://computeexpresslink.org/blog/micron-demonstrates-memory-sharing-across-a-cxl-fabric-at-supercomputing-2024-sc24-3192/) - Today, data centers face challenges to keep up with the growing requirements of AI and HPC workloads. Increased compute and memory demand for AI applications highlights a major challenge in the market known as the “memory wall.” In short, the memory wall describes the growing gap between compute capability and memory capacity and bandwidth in
- [Rambus, VIAVI, and Samtec Demonstrate CXL® over Optics PoC at Upcoming SC24](https://computeexpresslink.org/blog/rambus-viavi-and-samtec-demonstrate-cxl-over-optics-poc-at-upcoming-sc24-3171/) - The disruption of GenAI over the last few years has forced system architects and hardware designers to rethink data center topologies. While AI model sizes and compute capability are growing exponentially, I/O throughput and memory access are growing linearly. These trends create an unsustainable gap that needs to be addressed across the stack starting from
- [Discover Deployment-Ready CXL Solutions at Supercomputing 2024 (SC24)](https://computeexpresslink.org/blog/discover-deployment-ready-cxl-solutions-at-supercomputing-2024-sc24-3161/) - The CXL Consortium will be on-site at Supercomputing 2024 (SC24) to demonstrate how CXL technology solves memory bottlenecks for memory-intensive and memory-elastic workloads while also enhancing AI / ML workloads with expanded memory access. Our member companies are excited to showcase CXL solutions available in the market today capable of addressing performance gaps between compute
- [CXL Momentum Accelerates at FMS 2024](https://computeexpresslink.org/blog/cxl-momentum-accelerates-at-fms-2024-3068/) - By: Anil Godbole and Kurtis Bowman, CXL Consortium MWG Co-Chairs CXL technology made a huge splash at FMS: the Future of Memory and Storage 2024 as the Consortium and our member companies highlighted the growing CXL ecosystem. The rapid evolution of the CXL specification from 1.1 to 3.X in a short span of four
- [“Exploring CXL® Use Cases and Implementations” Webinar Q&A Recap](https://computeexpresslink.org/blog/exploring-cxl-use-cases-and-implementations-webinar-qa-recap-3043/) - CXL Consortium member companies Astera Labs, Samtec, and UnifabriX recently hosted a webinar exploring the use cases and implementations of CXL technology. Ahmed Medhioub (Astera Labs), Matthew Burns (Samtec), and Oren Benisty (UnifabriX) each highlighted their company’s CXL solutions based on the CXL 1.1 and 2.0 specifications available in the market today as well as
- [CXL FMS 2024 Video Demos](https://computeexpresslink.org/uncategorized/cxl-fms-2024-video-demos-2991/) - Amphenol – Expanding CXL Connectivity with Amphenol 32.0+ Gbps Optical QSFP-DDAmphenol demonstrates 32+ Gbps over optical QSFP-DD (x8 lanes) to provide several key advantages over traditional copper cables, in partnership with fellow CXL members GigaIO and Microchip. Optical x16 links will allow compute nodes to be distributed across multiple racks in the data center, greatly increasing
- [Join the CXL Consortium at the Future of Memory and Storage (FMS) 2024 Event](https://computeexpresslink.org/blog/join-the-cxl-consortium-at-the-future-of-memory-and-storage-fms-2024-event-2964/) - The CXL Consortium is excited to return to the upcoming Future of Memory and Storage (FMS) 2024 event from August 6-8 in Santa Clara, CA. CXL technology experts and Consortium representatives will be onsite highlighting the expanding CXL device ecosystem and use cases while also sharing insights into the future of CXL. Join us during the CXL
- [Understanding CXL RAS Capabilities: Enhancing Performance and Reliability Across Modern Data Centers](https://computeexpresslink.org/blog/understanding-cxl-ras-capabilities-enhancing-performance-and-reliability-across-modern-data-centers-2947/) - Introduction The ever-growing demand for performance and scalability in modern data centers has fueled breakthroughs in computing architectures. Among the most significant advancements in this field is the introduction of Compute Express Link® (CXL®), which dramatically boosts data transfer speeds and enables tight coupling between CPUs, workload accelerators, and memory expansion devices. In this article,
- [CXL Community Gathers at Inaugural DevCon 2024](https://computeexpresslink.org/blog/cxl-community-gathers-at-inaugural-devcon-2024-2927/) - In May, CXL Consortium Working Group Chairs and Consortium members gathered at the Santa Clara Marriott in California for the first-ever CXL Developers Conference. The event would not have been possible – and certainly less engaging – without the support of our sponsors: Alphawave Semi, Cadence, MemVerge, Montage Technology, Panmnesia, Samsung, SerialTek, SK Hynix, Teledyne
- [CXL Consortium Compliance Program Overview: Integrator’s List & Feature Testing](https://computeexpresslink.org/webinars/cxl-consortium-compliance-program-overview-integrators-list-feature-testing-314/)
- [Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL® (Compute Express Link®)](https://computeexpresslink.org/blog/integrity-and-data-encryption-ide-trends-and-verification-challenges-in-cxl-compute-express-link-2797/) - By: Narasimha Babu GVL, Scientist, Synopsys Threat Mitigation in CXL Data, Data, and Data everywhere! Data processing is no longer localized but distributed. In the use case, “Software as a Service (SaaS)”, cloud-based computing models place increasingly demanding needs for data security with the ability to set up, control and execute within Trusted Execution
- [Technical Trainings and Live Demonstrations to be Featured at Inaugural CXL DevCon 2024 Member Event](https://computeexpresslink.org/blog/technical-trainings-and-live-demonstrations-to-be-featured-at-inaugural-cxl-devcon-2024-member-event-2766/) - The CXL Consortium is pleased to host the first-ever CXL Developers Conference (DevCon), taking place April 30 – May 1, 2024, in Santa Clara, CA. This inaugural event represents a unique opportunity for Consortium members to learn from CXL experts by attending technical trainings and use case scenario presentations while viewing CXL technology-based demonstrations and
- [CXL Consortium hosts first Pre-FYI compliance event](https://computeexpresslink.org/blog/cxl-consortium-hosts-first-pre-fyi-compliance-event-1139/) - Testing for CXL 1.1 devices with support for CXL 2.0 equipment CXL Consortium hosted the first CXL® Pre-FYI compliance event on July 12-14, 2022, in Beaverton, Oregon. All CXL Consortium Member companies with a CXL product ready for testing were given the opportunity to participate in this event. The Consortium believes that compliance and interoperability
- [Introduction to Compute Express Link (CXL): The CPU-To-Device Interconnect Breakthrough](https://computeexpresslink.org/blog/introduction-to-compute-express-link-cxl-the-cpu-to-device-interconnect-breakthrough-2313/) - Compute Express Link (CXL) technology was unveiled in March 2019 and quickly became the talk of the High Performance Computing (HPC) and Enterprise Cloud industries with the release of CXL Specification 1.0. The intent of this Blog posting is to provide basic information on CXL and provide pointers to additional information. In short, CXL is
- [Incorporation and Expanded Board of Directors Propel the CXL Consortium Toward a Bright New Future](https://computeexpresslink.org/blog/incorporation-and-expanded-board-of-directors-propel-the-cxl-consortium-toward-a-bright-new-future-2317/) - Six months after our initial launch, the CXL Consortium™ has officially incorporated and added five new board members to its roster. This solidified infrastructure will enable the organization to drive new Compute Express Link™ (CXL) developments and facilitate overall industry adoption. Our initial promoter companies, Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei,
- [Industry Sounds Off on the Emergence of Compute Express Link™ (CXL™)](https://computeexpresslink.org/blog/industry-sounds-off-on-the-emergence-of-compute-express-link-cxl-2320/) - Compute Express Link™ (CXL™) technology made its initial public debut in March 2019, when industry leaders – Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft – came together to jointly develop and promote this exciting new high performance data center interconnect standard. Since then, the CXL™ Consortium has announced
- [Join Us: "Introduction to Compute Express Link™" Webinar on December 12](https://computeexpresslink.org/blog/join-us-introduction-to-compute-express-link-webinar-on-december-12-2322/) - REGISTER HERE FOR THE WEBINAR Compute Express Link™ (CXL™) was first initiated by industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft in March of 2019. The goal for the organization was to form an open industry standard group for the development of technical specifications that facilitate
- [CXL™ Consortium Makes a Splash at SC19](https://computeexpresslink.org/blog/cxl-consortium-makes-a-splash-at-sc19-2325/) - CXL™ Consortium members joined forces to promote Compute Express Link™ (CXL) technology at Supercomputing Conference 2019 (SC19) in Denver last month. Held at the Colorado Convention Center from November 17-22, SC19 saw many of our member companies displaying our ‘Proud Member’ signs on the exhibit floor, highlighting member companies’ individual roles and raising visibility of
- [CXL™ Consortium Membership Benefits](https://computeexpresslink.org/blog/cxl-consortium-membership-benefits-2327/) - Join Our Rapidly Expanding Organization and Learn How to Get Involved! The one-year mark of the Compute Express Link™ announcement of intent to incorporate is quickly approaching. We have hit the ground running with incredible momentum in our working groups which are working diligently to deliver Compute Express Link technology to our community and the
- [You Asked, We Answered! Answers to Your CXL™ Consortium Webinar Questions](https://computeexpresslink.org/blog/you-asked-we-answered-answers-to-your-cxl-consortium-webinar-questions-2329/) - I recently moderated our first CXL Consortium webinar, “Introduction to Compute Express Link™.” We had many great questions come in during the Q&A portion, but ran out of time to get to them all. To address them, we’ve provided answers to your questions below. If you were unable to join the live session, the full
- [The CXL™ Consortium Primed to Make a Big Impact at 2020 Industry Events](https://computeexpresslink.org/blog/the-cxl-consortium-primed-to-make-a-big-impact-at-2020-industry-events-2333/) - This March marks the first anniversary of the public debut for the CXL Consortium – launched to advance the Compute Express Link™ (CXL™) standard. This new high-speed CPU-to-Device and CPU-to-Memory interconnect accelerates next-generation data center performance. Since the release of the CXL 1.1 specification, we have been making headline news in several prominent publications such
- [Join Us: “Compute Express Link™ (CXL™): Exploring Coherent Memory and Innovative Use Cases” Webinar](https://computeexpresslink.org/blog/join-us-compute-express-link-cxl-exploring-coherent-memory-and-innovative-use-cases-webinar-2335/) - REGISTER HERE FOR THE WEBINAR Register now for our next educational webinar on CXL technologies, “Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases.” CXL is the new high-speed CPU-to-Device and CPU-to-Memory interconnect that accelerates next-generation data center performance. “Exploring Coherent Memory and Innovative Use Cases” Webinar Details: CXL technology maintains a
- [Compute Express Link™ 1.1 Specification: Now Available to Members](https://computeexpresslink.org/blog/compute-express-link-1-1-specification-now-available-to-members-2339/) - The Compute Express Link™ (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. CXL is based on the PCI Express® (PCIe®) 5.0 physical layer infrastructure as shown in Figure 1. Figure 1: Compute Express
- [Questions from the Compute Express Link™ Exploring Coherent Memory and Innovative Use Cases Webinar](https://computeexpresslink.org/blog/questions-from-the-compute-express-link-exploring-coherent-memory-and-innovative-use-cases-webinar-2341/) - I recently moderated the “Exploring Coherent Memory and Innovative Use Cases” webinar, during which we explored many topics. These included: How CXL technology maintains coherency between the CPU memory space and attached device memory The methods by which CXL views memory components namely processors, cashing agents and systems The many uses cases of CXL We
- [DMTF and CXL Consortium Establish Work Register](https://computeexpresslink.org/blog/dmtf-and-cxl-consortium-establish-work-register-2344/) - As part of DMTF’s Alliance Partner program, the organization and the Compute Express Link (CXL) Consortium have agreed to a new work register, which outlines areas of technical collaboration between the two organizations. Compute Express Link™ is a CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators.
- [Calling All Members: CXL™ Specification Technical Training Registration Now Open](https://computeexpresslink.org/blog/calling-all-members-cxl-specification-technical-training-registration-now-open-2346/) - The CXL™ Marketing Working Group is working with the Technical Task Force to host a members-only virtual technical training which will cover the CXL 1.1 specification and the in-progress 2.0 specification. Members of the Technical Task Force will provide in-depth courses on selected chapters of the specifications. Following their presentations, the presentation will be open
- [The Benefits of Serial-Attached Memory with Compute Express Link™](https://computeexpresslink.org/blog/the-benefits-of-serial-attached-memory-with-compute-express-link-2349/) - Introduction With the ever-increasing compute and memory bandwidth demands on data center servers, system implementors continuously strive to find novel techniques to provide higher performance for a wide range of application workloads while maintaining or even decreasing the cost of new infrastructure. The fundamental challenge of traditional servers results from being locked to specific memory
- [Compliance and Interoperability: Critical Indicators of Technology Success](https://computeexpresslink.org/blog/compliance-and-interoperability-critical-indicators-of-technology-success-2351/) - Today there are several standards developing organizations (SDOs) that create industry specifications for new technologies that meet the evolving needs of consumers. Some of the most successful technologies that have been broadly adopted into billions of devices include USB, Wi-Fi, and PCI Express®. What did these SDOs do to achieve this level of success? There
- [Join Us: “Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions” Webinar](https://computeexpresslink.org/blog/join-us-compute-express-link-cxl-memory-challenges-and-cxl-solutions-webinar-2353/) - We are continuing our educational webinars on CXL and our next one is focused on how CXL can address the memory challenges designers are facing with new emerging applications. I encourage you to register for our upcoming webinar “Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions” to learn more about the benefits of using
- [Compute Express Link: UEFI and ACPI Specification Enhancement Recommendations](https://computeexpresslink.org/blog/compute-express-link-uefi-and-acpi-specification-enhancement-recommendations-2355/) - Compute Express Link™ (CXL™) is a new, high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. UEFI and ACPI specifications provide standard interfaces for discovering new system attributes and as such need to be extended for discovering, enumerating and configuring CXL devices and CXL-capable systems. Many members of the UEFI Forum are
- [System Considerations for Compute Express Link® Attached Devices - form factors, connectors, backplanes](https://computeexpresslink.org/blog/system-considerations-for-compute-express-link-attached-devices-form-factors-connectors-backplanes-2363/) - Introduction Compute Express Link™ (CXL™) addresses the growing memory bandwidth and capacity needs for processors to accelerate high-speed computing applications, such as artificial intelligence, cloud computing and machine learning. The industry is quickly transitioning to take advantage of the capabilities enabled by this new protocol and the fast-path to adoption is in no small part
- [Questions from the Compute Express Link® Memory Challenges and CXL® Solutions Webinar](https://computeexpresslink.org/blog/questions-from-the-compute-express-link-memory-challenges-and-cxl-solutions-webinar-2366/) - We recently presented the “Memory Challenges and CXL Solutions” webinar, where we explored the current trends and challenges of memory and shared how CXL can address the challenges that designers are facing with new emerging applications. We received many great questions during the Q&A portion, but we ran out of time to address them all.
- [CXL® Consortium Celebrates its First Anniversary](https://computeexpresslink.org/blog/cxl-consortium-celebrates-its-first-anniversary-2370/) - Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. This September marks the first anniversary of the incorporation of the CXL™ Consortium which was launched by industry leaders to drive adoption and continue the advancement of CXL technology. This first year has seen a number of significant milestones
- [SNIA and CXL® Consortium Form Strategic Alliance](https://computeexpresslink.org/blog/snia-and-cxl-consortium-form-strategic-alliance-2372/) - The Storage Networking Industry Association (SNIA) and the CXL™ Consortium have formed a strategic alliance to enable the education and to support the subsequent adoption of their technologies by interested individuals, including developers, implementors, and end users. SNIA is a non-profit organization comprised of member companies. A globally recognized and trusted authority, SNIA’s mission is
- [Compute Express Link® 2.0 Specification Now Available!](https://computeexpresslink.org/blog/compute-express-link-2-0-specification-now-available-2374/) - On behalf of the CXL Consortium Technical Task Force, we’re pleased to share that the Compute Express Link™ (CXL™) 2.0 specification has been completed and is now available for public download on the Consortium’s specification page. A special thank you to our dedicated technical work group members who helped bring this significant achievement to fruition.
- [FMS 2020 and SC’20 Recap: CXL Consortium Highlights](https://computeexpresslink.org/blog/fms-2020-and-sc20-recap-cxl-consortium-highlights-2376/) - This year has been a little different. Due to COVID-19, industry events were forced to cancel, postpone and/or go virtual. The CXL Consortium shifted our focus to virtual opportunities in order to further promote CXL technology – utilizing virtual Technical Training and educational webinars. Last month, the CXL Consortium had an opportunity to participate in
- [Questions from the Webinar: Introducing the Compute Express Link® 2.0 Specification](https://computeexpresslink.org/blog/questions-from-the-webinar-introducing-the-compute-express-link-2-0-specification-2378/) - Last December, we presented a webinar titled “Introducing the Compute Express Link™ 2.0 Specification.” The presentation explored the new features and usage models of the CXL 2.0 specification including switching and pooling, hot-plug, fabric manager API, persistent memory, security and more. The webinar recording is available on BrightTALK and YouTube. Also, the presentation is available
- [An Overview of Reliability, Availability, and Serviceability (RAS) in CXL® 2.0 White Paper Now Available](https://computeexpresslink.org/blog/an-overview-of-reliability-availability-and-serviceability-ras-in-cxl-2-0-white-paper-now-available-2380/) - To complement the CXL 2.0 Specification, the CXL Consortium Software & Systems Workgroup published the Overview of RAS in CXL 2.0 White Paper. This white paper shares details on the key RAS capabilities of the CXL 2.0 Specification and provides some recommendations of their usage. RAS remains an important consideration in server design, deployment and
- [Upcoming Webinar: CXL® 2.0 Specification – Memory Pooling](https://computeexpresslink.org/blog/upcoming-webinar-cxl-2-0-specification-memory-pooling-2383/) - Join us for the upcoming “Compute Express Link™ 2.0 Specification: Memory Pooling” educational webinar airing Tuesday, March 23, 2021, from 9-10 am PT. Last November, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full backward compatibility with
- [CXL Presents: Join Us at the SNIA Persistent Memory and Computational Storage Summit](https://computeexpresslink.org/blog/cxl-presents-join-us-at-the-snia-persistent-memory-and-computational-storage-summit-2385/) - The Compute Express Link™ (CXL™) Consortium will have several presentations at the 8th Annual SNIA Persistent Memory and Computational Storage Summit, taking place virtually April 21-22, 2021. I encourage you to register to attend the conference to gain insight into the future of technology and trends from leading storage and memory experts. View the complete
- [Animated Videos Illustrate CXL® Technology and CXL 2.0 Key Features](https://computeexpresslink.org/blog/animated-videos-illustrate-cxl-technology-and-cxl-2-0-key-features-2387/) - The CXL™ Consortium has released two animated videos on the official CXL YouTube Channel introducing the Compute Express Link™ protocol and the new features of the CXL 2.0 specification. The straightforward and engaging format of these videos brings the viewer into the landscape of CXL technology and showcases its features. The Introduction to Compute Express
- [CXL® 2.0 Specification: Memory Pooling – Questions from the Webinar Part 2](https://computeexpresslink.org/blog/cxl-2-0-specification-memory-pooling-questions-from-the-webinar-part-2-2391/) - The recent CXL™ Consortium webinar provided a deep dive into the memory pooling features of the CXL 2.0 specification and introduced the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions. In the previous webinar Q&A blog post, we answered questions from attendees about
- [Compute Express Link® (CXL®) 2.0 Specification: Memory Pooling – Questions from the Webinar Part 1](https://computeexpresslink.org/blog/compute-express-link-cxl-2-0-specification-memory-pooling-questions-from-the-webinar-part-1-2389/) - The CXL™ 2.0 specification, released in November 2020, includes support for a number of new features, including memory pooling for increased memory utilization while providing memory capacity on demand. In the recent CXL Consortium webinar, we explored how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device
- [Upcoming Webinar: Compute Express Link® (CXL®): Supporting Persistent Memory](https://computeexpresslink.org/blog/upcoming-webinar-compute-express-link-cxl-supporting-persistent-memory-2393/) - Join industry experts from Intel and SK hynix for the upcoming CXL™ Consortium webinar: “Compute Express Link™ (CXL™): Supporting Persistent Memory” airing on June 15 at 4:00 pm PDT with a replay presentation the following day at 9:00 am PDT. The CXL 2.0 specification, released in November 2020, introduced support for switching, memory pooling, and
- [CXL® Consortium Member Spotlight: Arm](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-arm-2398/) - CXL Consortium member company Arm recently participated in a Q&A session to discuss its involvement in the consortium, benefits of membership, and the impact of CXL within the storage and memory industry. Read the full Q&A session with Arm below. Why did Arm decide to join the CXL™ Consortium? Arm represents the interest of the
- [CXL® Consortium and Gen-Z Consortium™ MoU Update: A Path to Protocol](https://computeexpresslink.org/blog/cxl-consortium-and-gen-z-consortium-mou-update-a-path-to-protocol-2400/) - Since we announced the Memorandum of Understanding (MoU) agreement between the CXL™ Consortium and Gen-Z Consortium™ last year, the organizations’ joint working group has been busy defining three specific use cases – from an initial pool of over 30 – that will benefit from a CXL to Gen-Z bridge. Compute Express Link™ and Gen-Z are
- [CXL® Consortium Member Spotlight: Cadence](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-cadence-2402/) - CXL Member Company Cadence Design Systems recently took part in a Q&A session which addressed its involvement in the organization, expertise in the IP ecosystem, and benefits of CXL membership. Find the full Q&A session below. Why did Cadence decide to join the CXL™ Consortium? Cadence shares the CXL Consortium’s vision that a new interconnect
- [CXL® Consortium Member Spotlight: Synopsys](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-synopsys-2405/) - CXL Member Company Synopsys recently took part in a Q&A session with CXL Consortium to discuss membership benefits, industry expertise, and use cases for CXL technology. Learn more about Synopsys and its participation in the CXL Consortium by reading the full Q&A session below. Why did Synopsys decide to join the CXL™ Consortium? We joined
- [Questions from the Compute Express Link® (CXL®): Supporting Persistent Memory Webinar](https://computeexpresslink.org/blog/questions-from-the-compute-express-link-cxl-supporting-persistent-memory-webinar-2407/) - The recent webinar on “Compute Express Link™ (CXL™): Supporting Persistent Memory” explored how the CXL specification has evolved to support persistent memory devices and the established software model. The webinar also covered how enhancements to the CXL protocol, error handling and standardized configuration interface enable innovative designs that are based on a variety of non-volatile
- [CXL® Consortium Member Spotlight: Elastics.cloud](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-elastics-cloud-2409/) - CXL™ Consortium member company Elastics.cloud took part in a recent Q&A session to discuss their involvement in the consortium, advantages of membership, and their expertise within the computing infrastructure market. Read the full Q&A session below. Can you share a brief introduction of Elastics.cloud? Elastics.cloud, Inc. is a systems, semiconductor, hardware and software systems company,
- [CXL® Consortium Member Spotlight: Facebook](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-facebook-2411/) - CXL™ Consortium member company Facebook recently participated in a Q&A session to discuss its participation in the consortium, advantages of CXL membership, and the impact of CXL on the next generation workloads. Read the full Q&A session with Facebook below. Why did Facebook decide to join the CXL™ Consortium? Facebook’s products empower more than 3
- [Upcoming Webinar: Compute Express Link® (CXL®) Link-level Integrity and Data Encryption (CXL IDE)](https://computeexpresslink.org/blog/upcoming-webinar-compute-express-link-cxl-link-level-integrity-and-data-encryption-cxl-ide-2413/) - Join us for the upcoming CXL™ Consortium webinar: “Compute Express Link™ (CXL™) Link-level Integrity and Data Encryption (CXL IDE)” airing on September 30 at 8 am PT. The CXL 2.0 specification enhances the security mechanism from CXL 1.1 and 1.0 by adding link-level Integrity and Data Encryption (CXL IDE) to provide confidentiality, integrity and replay
- [CXL® Consortium and PCI-SIG® Announce Marketing MOU Agreement](https://computeexpresslink.org/blog/cxl-consortium-and-pci-sig-announce-marketing-mou-agreement-2415/) - The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations. This MOU establishes a liaison framework between the two organizations to ensure consistent joint messaging and marketing across areas of mutual interest. PCI-SIG is an association of 800+ industry companies committed to advancing its non-proprietary peripheral component
- [CXL® Consortium Upcoming Industry Events](https://computeexpresslink.org/blog/cxl-consortium-upcoming-industry-events-2417/) - The CXL™ Consortium is excited to be participating in several industry events, including virtual events such as Storage Developer Conference, Arm DevSummit, and Intel Innovation as well as hybrid events OCP Global Summit and Supercomputing 21. Upcoming Events in 2021 Below is a list of confirmed industry events and speaking opportunities the CXL Consortium will
- [CXL® Consortium Member Spotlight: IntelliProp](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-intelliprop-2419/) - CXL™ Consortium member company IntelliProp recently participated in a Q&A session to discuss CXL’s impact within the storage and memory industry, IntelliProp’s participation in CXL Consortium working groups and ideal use cases for CXL technology. Find the full Q&A with IntelliProp below. Can you share a brief introduction of IntelliProp? IntelliProp started in 1998 as
- [CXL® Consortium Member Spotlight: Samsung](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-samsung-2422/) - CXL™ Consortium member company Samsung participated in a recent Q&A session to discuss advantages of CXL Consortium membership, use cases for CXL technology and its expertise in memory and storage technologies. Read the full Q&A session with Samsung below. Why did Samsung decide to join the CXL™ Consortium? Samsung intends to lead the memory industry
- [CXL® Consortium Member Spotlight: Numascale](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-numascale-2424/) - CXL™ Consortium member company Numascale recently participated in a Q&A session to discuss advantages of consortium membership, Numascale’s expertise in developing cache coherent interconnect technology and the impact of CXL technology on future datacenters. Read the full Q&A with Numascale below. Can you share a brief introduction of Numascale? Numascale is the leading independent provider
- [Exploring the Future: CXL® Consortium & Gen-Z Consortium Sign Letter of Intent to Advance Interconnect Technology](https://computeexpresslink.org/blog/exploring-the-future-cxl-consortium-gen-z-consortium-sign-letter-of-intent-to-advance-interconnect-technology-2426/) - High performance computing continues to evolve—meeting the ever-increasing demand for high efficiency, low-latency, rapid and seamless processing. The Gen-Z Consortium was founded in 2016 to create a next-generation fabric capable of bridging existing solutions while enabling new, unbounded innovation in an open, non-proprietary standards body. In 2019, the CXL™ Consortium launched to deliver Compute Express
- [Questions from the “Compute Express Link® (CXL®) Link-level Integrity and Data Encryption" Webinar](https://computeexpresslink.org/blog/questions-from-the-compute-express-link-cxl-link-level-integrity-and-data-encryption-webinar-2428/) - The recent “Compute Express Link™ (CXL™) Link-level Integrity and Data Encryption (CXL IDE)” webinar explored CXL IDE usage models and how security is managed across CXL.io, CXL.mem, CXL.cache and CXL Switches. The webinar also explored a device’s responsibility to maintain security. If you missed the live webinar, the recording is available on BrightTALK and YouTube.
- [Upcoming Webinar: An Overview of the Compute Express Link® (CXL®) 2.0 ECN](https://computeexpresslink.org/blog/upcoming-webinar-an-overview-of-the-compute-express-link-cxl-2-0-ecn-2430/) - We invite you to register for the upcoming CXL™ Consortium webinar: “An Overview of the Compute Express Link™ (CXL™) 2.0 ECN” airing live on December 9 at 9:00 am PT. Released in November 2020, the CXL 2.0 specification introduced support for switching, memory pooling and for persistent memory. The specification also preserved industry investments by
- [CXL® Consortium Member Spotlight: Mobiveil](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-mobiveil-2432/) - CXL™ Consortium member company Mobiveil recently took part in a Q&A session with CXL Consortium to discuss CXL’s impact within the storage and memory industry, advantages of CXL membership and ideal use cases for CXL technology. Continue reading the full Q&A session to learn more about Mobiveil and its involvement within the consortium. Can you
- [Compute Express Link™ (CXL™) 2.0 ECN: Significant Improvements in device management, RAS, Security and more!](https://computeexpresslink.org/blog/compute-express-link-cxl-2-0-ecn-significant-improvements-in-device-management-ras-security-and-more-2022/) - The CXL™ Consortium released the CXL 2.0 specification in November 2020, which introduced switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility with CXL 1.1. This year, the technical working groups worked diligently to enhance the CXL 2.0 specification and published 14 Engineering Change Notices
- [CXL Consortium Makes a Splash at Supercomputing 2021 (SC21)](https://computeexpresslink.org/blog/cxl-consortium-makes-a-splash-at-supercomputing-2021-sc21-2013/) - Supercomputing 2021 (SC21) took place recently in St. Louis, Missouri, and was the CXL™ Consortium’s first in-person industry event since its formation in 2019. The Consortium stood out showcasing the first public demonstrations of Compute Express Link™ (CXL™) technology from member companies, a Birds of a Feather session in collaboration with Gen-Z Consortium™ and SNIA,
- [Questions from the “An Overview of the Compute Express Link™ (CXL™) 2.0 ECN” Webinar](https://computeexpresslink.org/blog/questions-from-the-an-overview-of-the-compute-express-link-cxl-2-0-ecn-webinar-2009/) - The CXL 2.0 specification introduced support for switching, memory pooling, and for persistent memory – all while preserving industry investments by supporting full backward compatibility. Based on member feedback, CXL 2.0 ECNs made significant improvements to the specifications in the areas of device management, RAS, Security, memory interleaving and others. “An Overview of the Compute
- [CXL™ Consortium Member Spotlight: Rambus](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-rambus-2007/) - CXL™ Consortium member company Rambus participated in a recent Q&A session to discuss CXL’s impact on the evolution of the data center, Rambus’ expertise in CXL interface subsystems, and ideal use cases for CXL technology. Find the full Q&A session with Rambus below. Can you share a brief introduction of Rambus? Rambus makes industry-leading chips
- [CXL™ Consortium Member Spotlight: GigaIO](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-gigaio-2005/) - CXL™ Consortium member company GigaIO participated in a recent Q&A session to discuss GigaIO’s participation in the Consortium, CXL’s impact in the memory and storage industry and future use cases for CXL technology. Continue reading for the full Q&A session with GigaIO below. Can you share a brief introduction of GigaIO? GigaIO is democratizing access
- [Upcoming Webinar: Introduction to the Compute Express Link™ (CXL™) Fabric Manager](https://computeexpresslink.org/blog/upcoming-webinar-introduction-to-the-compute-express-link-cxl-fabric-manager-2001/) - We invite you to register for the upcoming CXL™ Consortium webinar: “Introduction to the Compute Express Link™ (CXL™) Fabric Manager” airing live on Tuesday, March 22 from 10:00 – 11:00 am PT. The CXL 2.0 specification introduces a standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch
- [CXL™ Consortium Member Spotlight: SK hynix](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-sk-hynix-1999/) - CXL™ Consortium member company SK hynix recently participated in a Q&A to discuss the development of the next-generation memory solutions, participation in CXL Consortium workgroups and how CXL enables memory capacity expansion. Find the full Q&A with SK hynix below. Can you share a brief introduction of SK hynix? SK hynix is a leading corporation
- [CXL® Consortium Member Spotlight: Tanzanite Silicon Solutions](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-tanzanite-silicon-solutions-1156/) - CXL® Consortium member company Tanzanite Silicon Solutions recently took part in a Q&A session to discuss Tanzanite’s experience in the industry, the benefits of CXL Consortium membership, and how CXL technology will enable a variety of use cases in the cloud, enterprise, and at the edge. Continue reading the full Q&A interview to learn more
- [Questions from the “Introduction to the Compute Express Link® (CXL®) Fabric Manager” Webinar](https://computeexpresslink.org/blog/questions-from-the-introduction-to-the-compute-express-link-cxl-fabric-manager-webinar-1152/) - The “Introduction to the Compute Express Link® (CXL®) Fabric Manager” webinar explored the CXL Fabric Manager (FM) and Multi-Logical Device (MLD) management and detailed the Component Command Interface (CCI) transport protocols, background operations and categories of requests. If you missed the live webinar, the recording is available on BrightTALK and YouTube. The presentation is also
- [CXL® Consortium Member Spotlight: Microchip](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-microchip-1149/) - CXL® Consortium member company Microchip Technology Inc. participated in a recent Q&A session to discuss its contributions in the Consortium, use cases that will be ideal targets for CXL technology and CXL’s impact on the future memory and storage industry. Continue reading for the full Q&A session with Microchip Technology Inc. below. Can you share
- [Upcoming Webinar: CXL 1.1 vs. CXL 2.0 – What’s the difference?](https://computeexpresslink.org/blog/upcoming-webinar-cxl-1-1-vs-cxl-2-0-whats-the-difference-1145/) - Join the upcoming webinar: “CXL 1.1 vs. CXL 2.0 – What’s the difference?” airing live on Wednesday, June 15 from 9:00 – 10:00 am PT. Compute Express Link® (CXL®) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O
- [CXL® Consortium Member Spotlight: Avery Design Systems](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-avery-design-systems-1142/) - CXL® Consortium member company Avery Design Systems recently participated in a Q&A session to discuss the benefits of CXL Consortium membership, its contributions to CXL compliance and ideal targets for CXL technology. Why did Avery decide to join the CXL Consortium? We joined the CXL Consortium to enable our support of the early adopter ecosystem
- [Questions from the “CXL 1.1 vs. CXL 2.0 – What’s the difference?” Webinar](https://computeexpresslink.org/blog/questions-from-the-cxl-1-1-vs-cxl-2-0-whats-the-difference-webinar-1135/) - The “CXL 1.1 vs. CXL 2.0 – What’s the difference?” webinar shared an overview of the CXL 1.1 specification and explored the enhancements made in CXL 2.0 focusing on switching, memory pooling, Single Logical (SLD) vs. Multiple Logical Devices (MLD), and fabric management. The webinar also covered managed hot-plug, memory QoS telemetry, speculative reads, and
- [Engage with CXL experts and members at Flash Memory Summit 2022](https://computeexpresslink.org/blog/engage-with-cxl-experts-and-members-at-flash-memory-summit-2022-1130/) - Don’t miss the chance for presentations and updates on Compute Express Link® (CXL®) 3.0 specification The CXL Consortium looks forward to engaging with the storage community at the upcoming Flash Memory Summit 2022 from August 2-4 at the Santa Clara Convention Center. Our CXL experts and members of the CXL Consortium will be sharing updates
- [CXL® Consortium Member Spotlight: Astera Labs](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-astera-labs-1127/) - CXL® Consortium member company Astera Labs recently participated in a Q&A session to discuss the benefits of CXL Consortium membership, its contributions to CXL and ideal targets for CXL technology. Can you share a brief introduction of Astera Labs? Astera Labs is a fabless and cloud-based semiconductor company developing purpose-built connectivity solutions to overcome performance
- [Upcoming CXL Consortium Webinar: CXL 3.0: Enabling composable systems with expanded fabric capabilities](https://computeexpresslink.org/blog/upcoming-cxl-consortium-webinar-1122/) - Join the latest CXL Consortium webinar, “CXL 3.0: Enabling composable systems with expanded fabric capabilities,” airing live, Thursday, October 6, from 9 – 10 am PT. Compute Express Link® (CXL®) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and
- [CXL Fabric Management](https://computeexpresslink.org/blog/cxl-fabric-management-1089/) - Introduction Compute Express Link® (CXL®) is an interconnect architected for memory expansion, heterogenous compute, and the disaggregation of system resources. Disaggregation with CXL provides efficient resource sharing and pooling while maintaining low latency and high bandwidth with cache-coherent load-store semantics. With the anticipation of CXL becoming ubiquitous in the data centers of tomorrow, the CXL
- [Insight into CXL 2.0 Security Features and Benefits](https://computeexpresslink.org/blog/insight-into-cxl-2-0-security-features-and-benefits-1085/) - The explosion of modern applications such as Artificial Intelligence, Machine Learning and deep learning is changing the very nature of computing and transforming businesses. These applications have opened myriad ways for companies to improve their business development processes, operations, security and provide better customer experiences. To support these applications, platforms are being designed to utilize
- [CXL® Consortium Demonstrates Industry-Leading Technology at Supercomputing 2022 (SC’22)](https://computeexpresslink.org/blog/cxl-consortium-demonstrates-industry-leading-technology-at-supercomputing-2022-sc22-1094/) - Supercomputing 2022 (SC’22) took place in Dallas from November 14-17 this year. The Compute Express Link® (CXL®) Consortium, along with a group of our member companies, showcased CXL technology demonstrations, hosted an Exhibitor Forum session, participated in a Birds of a Feather session, and received the Editors’ Choice Award for Best HPC Interconnect Product or
- [CXL® Consortium Member Spotlight: UniFabriX](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-unifabrix-1078/) - CXL Consortium member company UnifabriX recently participated in a Q&A session to discuss what prompted them to join the Consortium, its expertise, and exciting use cases for CXL technology. Can you share a brief introduction of UnifabriX? Founded in 2020, UnifabriX develops solutions that address the inefficiencies of large-scale system deployments, enabling datacenter operators to
- [CXL 3.0 Webinar Q&A Recap](https://computeexpresslink.org/blog/cxl-3-0-webinar-qa-recap-1075/) - Answering questions from the “CXL 3.0: Enabling composable systems with expanded fabric capabilities” webinar In October, the Co-Chair of the CXL Consortium Technical Task Force Dr. Debendra Das Sharma and MWG Contributor Danny Moore presented a webinar on CXL 3.0 to explore the new features and usage models in the latest specification. If you missed
- [Upcoming Webinar: A Look into the CXL® Device Ecosystem and the Evolution of CXL Use Cases](https://computeexpresslink.org/blog/upcoming-webinar-a-look-into-the-cxl-device-ecosystem-and-the-evolution-of-cxl-use-cases-1082/) - Register today to attend the CXL® Consortium webinar: “A Look into the CXL Device Ecosystem and the Evolution of CXL Use Cases,” airing live on Thursday, January 26, from 8 – 9 am PT. CXL (Compute Express Link®) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor
- [CXL® Consortium Member Spotlight: Xconn Technologies](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-xconn-technologies-1068/) - CXL Consortium gives members the opportunities to share their thoughts on being a CXL member. Xconn Technologies recently shared details around its contributions to the development of the CXL standard, the importance of CXL Consortium membership, and the future of CXL technology in the data center, cloud and AI computing, as well as HPC industries.
- [Questions from “A Look into the CXL® Device Ecosystem and the Evolution of CXL Use Cases” Webinar](https://computeexpresslink.org/blog/questions-from-a-look-into-the-cxl-device-ecosystem-and-the-evolution-of-cxl-use-cases-webinar-1065/) - Last month, CXL® Consortium Marketing Work Group Co-Chairs Kurt Lender and Kurtis Bowman presented a webinar covering the CXL device ecosystem and its use cases. The webinar also featured a Q&A panel of member representatives from AMD, Astera Labs, Elastics.cloud, Intel, IntelliProp, MemVerge, Samsung, Synopsys, Teledyne LeCroy, and UnifabriX. The panelists highlighted the CXL technology
- [DRAM Resource Scalability Enabled by CXL®](https://computeexpresslink.org/blog/dram-resource-scalability-enabled-by-cxl-1071/) - Introduction Computer server architectures continually evolve to support faster analytics with larger data sets delivered for analysis applications. Computing capabilities of Central Processing Units (CPUs), and Graphics Processing Units (GPUs) increase to enable modern applications such as Artificial Intelligence (AI) and Machine Learning (ML). As core counts for processors increase, there is more data being
- [CXL® Consortium Member Spotlight: Liqid](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-liqid-1058/) - CXL Consortium member Liqid recently shared their thoughts on the importance of CXL technology for the future of high-performance computing (HPC), artificial intelligence (AI), and data analytics verticals as well as its contribution to the Consortium and CXL standard development. Can you share a brief introduction of Liqid? Based in Westminster, CO, Liqid is a
- [Learn from CXL technology experts at Flash Memory Summit (FMS) 2023](https://computeexpresslink.org/blog/learn-from-cxl-technology-experts-at-flash-memory-summit-fms-2023-1055/) - The CXL Consortium is excited to participate in the upcoming Flash Memory Summit (FMS) 2023 event August 7-10 in Santa Clara, CA. CXL technology experts and Consortium members will be onsite sharing updates on CXL 3.0 - including the expanding device ecosystem and use cases - and insights into the future of CXL. Below is
- [Explaining CXL Memory Pooling and Sharing](https://computeexpresslink.org/blog/explaining-cxl-memory-pooling-and-sharing-1049/) - Compute Express Link® (CXL®) is a high-speed interconnect technology that enables efficient communication between processors, memory devices, and accelerators. CXL allows for both shared and pooled memory to serve different purposes. In this post, I will explain the importance of memory pooling and sharing and how CXL provides the much-needed solution. Shared memory is a
- [Compute Express Link Consortium, Inc. and CCIX Consortium, Inc. announce agreement for Consortium to receive CCIX Consortium Specifications and other CCIX Consortium assets](https://computeexpresslink.org/blog/compute-express-link-consortium-inc-and-ccix-consortium-inc-announce-agreement-for-consortium-to-receive-ccix-consortium-specifications-and-other-ccix-consortium-assets-1052/) - CCIX Consortium, Inc., (“CCIX” or the “CCIX Consortium”) and Compute Express Link Consortium, Inc. (“CXL” or the “CXL Consortium” ) announced that they have recently entered into an agreement pursuant to which CCIX Consortium’s specifications, trademarks, and other assets will be transferred to the CXL Consortium. The two organizations will be taking actions in accordance
- [Understanding the benefits of CXL® in datacenter environments – use cases and implementations](https://computeexpresslink.org/blog/understanding-the-benefits-of-cxl-in-datacenter-environments-use-cases-and-implementations-1046/) - Datacenter resources are increasingly strained by the escalation of high-performance computational workloads. Datacenters require heterogeneous processing and memory systems to support numerous applications, including servers, networking, storage, visual computing, edge infrastructure, and artificial intelligence. Rapid developments in computing infrastructure requirements are driving the need for a new interface that meets the increasing demands for high
- [Upcoming Webinar: CXL Consortium Compliance Program Overview: Integrators List & Feature Testing](https://computeexpresslink.org/blog/upcoming-webinar-cxl-consortium-compliance-program-overview-integrators-list-feature-testing-1024/) - Don’t miss the upcoming Compute Express Link® (CXL®) Consortium webinar: “CXL Consortium Compliance Program Overview: Integrators List & Feature Testing,” airing live on Thursday, September 7, from 9:00 – 9:45 am PT. Register for the webinar here. CXL Consortium member companies are developing a wide range of products and devices including CXL memory solutions, IP,
- [CXL® Memory Form-Factor Comparison: Examination of Form-Factors for this Growing Standard](https://computeexpresslink.org/blog/cxl-memory-form-factor-comparison-examination-of-form-factors-for-this-growing-standard-1027/) - Introduction Computer systems have used direct attached memory modules in the form of DIMMs for decades. These modules attach directly to the host motherboard and to the CPU using a parallel bus. Expanding the number of modules a system can utilize involves adding memory controllers and pins to the CPU which quickly becomes prohibitive. As
- [“CXL Consortium Compliance Program Overview: Integrators List & Feature Testing” Webinar Q&A Recap](https://computeexpresslink.org/blog/cxl-consortium-compliance-program-overview-integrators-list-feature-testing-webinar-qa-recap-521/) - The CXL® Consortium Compliance Working Group (CWG) Co-Chairs, Michael Hall and Nathan White, recently hosted a webinar covering the CXL Compliance Program, which enables compliance and interoperability testing for CXL devices, and the Consortium’s Integrators List as well as information on the recent CXL 1.1 and pre-FYI CXL 2.0 test event and upcoming Compliance Test
- [CXL® Consortium Member Spotlight: Panmnesia](https://computeexpresslink.org/blog/cxl-consortium-member-spotlight-panmnesia-518/) - Can you share a brief introduction of Panmnesia? Panmnesia is revolutionizing the world of Compute Express Link® (CXL®) technology by offering a comprehensive range of Intellectual Property (IP) solutions in hardware and software. Our unique offerings empower our customers to create specialized CXL products that deliver optimal performance and cost-effectiveness. Our IPs serve as the
- [Experience the Evolution of CXL Technology at SC’23](https://computeexpresslink.org/blog/experience-the-evolution-of-cxl-technology-at-sc23-1017/) - The CXL Consortium is excited to participate in the upcoming Supercomputing 2023 (SC’23) event in Denver, CO. CXL technology experts and Consortium member companies will demonstrate the evolution of the CXL specification, highlight use cases and the expansion of the CXL device ecosystem. View the comprehensive list of Consortium activities below: CXL Presentations Birds of
- [Upcoming Webinar: Introducing the CXL 3.1 Specification](https://computeexpresslink.org/blog/upcoming-webinar-introducing-the-cxl-3-1-specification-2021/) - Join the upcoming Compute Express Link® (CXL®) Consortium webinar: “Introducing the CXL 3.1 Specification,” airing live on Tuesday, February 20, from 9:00 – 10:00 am PT. Reserve your spot for the webinar here. In November 2023, the CXL Consortium announced the release of the CXL 3.1 specification, which builds on previous iterations to deliver improved
- [Showcasing the Evolution of CXL at Supercomputing 2023 (SC’23)](https://computeexpresslink.org/blog/showcasing-the-evolution-of-cxl-at-supercomputing-2023-sc23-2435/) - We were excited to return to the Supercomputing Conference (SC’23), located in Denver this year, to showcase the High Performance Computing benefits made capable with CXL technology. During the show, the CXL Consortium announced the release of the CXL 3.1 specification with improved fabric manageability to take CXL beyond the rack and enable disaggregated systems. The
- [CXL® Consortium Member Spotlight: SMART Modular Technologies](https://computeexpresslink.org/uncategorized/cxl-consortium-member-spotlight-smart-modular-technologies-2395/) - CXL™ Consortium member company SMART Modular Technologies took part in a recent Q&A session to discuss its involvement in the consortium, benefits of membership, and its capabilities in the storage and memory ecosystem. Read the full Q&A session below. Why did SMART Modular Technologies decide to join the CXL Consortium? We joined as a Contributor
- [“Introducing the CXL 3.1 Specification” Webinar Q&A Recap](https://computeexpresslink.org/blog/introducing-the-cxl-3-1-specification-webinar-qa-recap-2307/) - The CXL® Consortium recently hosted a webinar covering the CXL 3.1 specification, which builds on previous iterations to deliver improved fabric manageability, optimized resource utilization, and extended memory sharing and pooling. During the webinar, Mahesh Wagh, CXL Consortium Technical Task Force Co-Chair, and Rob Blankenship, Protocol Working Group Co-Chair, introduced the new features and use
- [Enabling CXL Memory Expansion Module with the CXL 3.1 Specification](https://computeexpresslink.org/blog/enabling-cxl-memory-expansion-module-with-the-cxl-3-1-specification-2298/) - Introduction The memory system industry is preparing for the productization of type 3 CXL® memory devices, targeting mass production within 2024 to align with the planned release of CXL 2.0 host systems. AI, Machine Learning, in-memory database & real-time analytics use cases, bandwidth, and capacity expansions require more than what the current memory system can
- [A look into the CXL device ecosystem and the evolution of CXL use cases](https://computeexpresslink.org/webinars/a-look-into-the-cxl-device-ecosystem-and-the-evolution-of-cxl-use-cases-317/)
- [Introducing CXL 3.0: Enabling composable systems with expanded fabric capabilities](https://computeexpresslink.org/webinars/introducing-cxl-3-0-enabling-composable-systems-with-expanded-fabric-capabilities-320/)
- [CXL 1.1 vs. CXL 2.0 – What’s the difference?](https://computeexpresslink.org/webinars/cxl-1-1-vs-cxl-2-0-whats-the-difference-323/)
- [Introduction to the Compute Express Link® (CXL®) Fabric Manager](https://computeexpresslink.org/webinars/introduction-to-the-compute-express-link-cxl-fabric-manager-326/)
- [An Overview of the Compute Express Link® (CXL®) 2.0 ECNs](https://computeexpresslink.org/webinars/an-overview-of-the-compute-express-link-cxl-2-0-ecns-330/)
- [Compute Express Link® (CXL®): Link-level Integrity and Data Encryption (CXL IDE)](https://computeexpresslink.org/webinars/compute-express-link-cxl-link-level-integrity-and-data-encryption-cxl-ide-333/)
- [Compute Express Link® (CXL®): Supporting Persistent Memory](https://computeexpresslink.org/webinars/compute-express-link-cxl-supporting-persistent-memory-336/)
- [Compute Express Link® 2.0 Specification: Memory Pooling](https://computeexpresslink.org/webinars/compute-express-link-2-0-specification-memory-pooling-339/)
- [Introducing the Compute Express Link® 2.0 Specification](https://computeexpresslink.org/webinars/introducing-the-compute-express-link-2-0-specification-341/)
- [Memory Challenges and CXL Solutions](https://computeexpresslink.org/webinars/memory-challenges-and-cxl-solutions-345/)
- [Exploring Coherent Memory and Innovative Use Cases](https://computeexpresslink.org/webinars/exploring-coherent-memory-and-innovative-use-cases-348/)
- [Introduction to Compute Express Link® (CXL)](https://computeexpresslink.org/webinars/introduction-to-compute-express-link-cxl-351/)

## Pages

- [Homepage](https://computeexpresslink.org/) - CXL 4.0 Specification Now AvailableThe CXL 4.0 Specification increases the bandwidth from 64GTs to 128GTs, adds support for bundled ports, and enhances memory RAS features. View the Press ReleaseUpcoming Industry EventsCXL Consortium representatives regularly support presentations and technology demonstrations during industry eventsView Upcoming Events Specifications Demos Videos Contact What's New Intel: CXL Memory Modes on
- [CXL Mini DevCon 2026 | August 3 | Santa Clara, CA](https://computeexpresslink.org/cxl-mini-devcon-2026/) - 2026 Agenda Registration Meet the Presenters Exhibitors & Sponsors Location & Lodging Parking & Transportation 2026 Agenda Registration Registration is complimentary for all CXL Consortium Members. Register to attend the event HERE.Cancellation Policy: Registrations canceled less than 7 days prior to the event will be assessed a $50 cancelation fee to offset facility costs. Please email admin@computeexpresslink.org to
- [Webinars](https://computeexpresslink.org/webinars/) - Featured Webinar Introducing the CXL 4.0 Specification October 8, 2025 Upcoming Webinars No future Webinars are scheduled. Past Webinars Vertical Optimization of the CXL Stack Apr 1, 2026 Zoom Webinar Introducing the CXL 4.0 Specification Dec 4, 2025 Zoom Webinar How CXL Transforms Server Memory Infrastructure Oct 8, 2025 BrightTALK Advantages of CXL Memory Sharing
- [CXL Specification Landing Page](https://computeexpresslink.org/cxl-specification-landing-page/) - 1. CXL® 4.0 Specification
- [CXL® Specification](https://computeexpresslink.org/cxl-specification/) - Specification Download Name(Required) First Last Email(Required) Company(Required)Consent(Required) I accept terms & conditions Download an Evaluation Copy of the CXL® 4.0 SpecificationPlease review the below and indicate your acceptance to receive immediate access to the Compute Express Link® Specification 4.0.COMPUTE EXPRESS LINK CONSORTIUM, INC.EVALUATION COPY AGREEMENT – as of February 12, 2026THIS EVALUATION COPY AGREEMENT (“Agreement”),
- [About CXL®](https://computeexpresslink.org/about-cxl/) - Compute Express Link® (CXL®) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus on target workloads
- [CXL Video Demos Shown at AI Infra Summit](https://computeexpresslink.org/cxl-video-demos-shown-at-ai-infra-summit/) - Visit the CXL Consortium at Booth no. 201 to view the CXL video demos and meet with CXL representatives to explore how CXL can boost your AI performance. Astera Labs and SMART Modular Technologies: Boost AI Inferencing with CXLIn this demo, Astera Labs and SMART Modular Technologies are showcasing how CXL memory expands memory capacity
- [Our Members](https://computeexpresslink.org/our-members/) - Keyword Search: Board of Directors Contributors Adopters Adopters 6Harmonics Inc. Accelerated Tech, Inc Accipiter Systems Inc Achronix Semiconductor Corporation Aclectic Systems Inc. ADATA Technology Co., Ltd ADTEC Corporation Aeponyx Inc. Agiliad Technologies Private Limited AIC Inc. AkroStar Technology Co.,Ltd. Allion AMI US Holdings Inc. Analogue Insight Anapass, Inc Anritsu Corporation AP Memory Corp, USA Apacer
- [FMS 2025 CXL Demos](https://computeexpresslink.org/fms-2025-cxl-demos/) - Visit our kiosk (Booth no. 725A) to view CXL video demos and explore how CXL can expand your memory footprint. Astera Labs and SMART Modular Technologies: Boost AI Inferencing with CXLIn this demo, Astera Labs and SMART Modular Technologies are showcasing how showcasing how CXL memory expands memory capacity and improves I/O efficiency, significantly boosting
- [Member News](https://computeexpresslink.org/member-news/) - For media inquiries or to request a briefing, contact press@computeexpresslink.org. Filters: Member Press Releases Members in the News Keyword Search: Member Press Releases Panmnesia Introduces Today’s and Tomorrow’s AI Infrastructure, Including a Supercluster Architecture... Jul 15, 2025 Teledyne LeCroy Unveils Next-Generation CXL™ 2.0 Device Validation Solution Oct 1, 2024 Teledyne LeCroy Announces Industry-First Compute Express Link™
- [Integrators List](https://computeexpresslink.org/integrators-list/) - The CXL Compliance Program has been developed as a benefit of Membership in the CXL Consortium. This program provides Members with opportunities to test the functionality and interoperability of end-products as defined in the CXL Specification and may contribute to a positive market experience by supporting the quality of products in the field. This program
- [Join CXL®](https://computeexpresslink.org/join-cxl/) - Two levels of membership have been defined for participation in CXL, with both levels receiving recognition on the public website.Contributor MembershipContributor membership with CXL allows your company to enjoy all of the benefits of the Adopter class plus: Participate in the technical working groupsInfluence the direction of the technologyAccess the intermediate (dot level) specificationsDues to participate
- [Industry Liaisons](https://computeexpresslink.org/industry-liaisons/) - DMTFAs part of DMTF’s Alliance Partner program, the organization and the Compute Express Link (CXL) Consortium agreed to a new work register, which outlines areas of technical collaboration between the two organizations. DMTF (formerly known as the Distributed Management Task Force) creates open manageability standards spanning diverse emerging and traditional IT infrastructures including cloud, virtualization, network, servers
- [End User License Agreement](https://computeexpresslink.org/complianceeula/) - END USER LICENSE AGREEMENT FOR USE OFCOMPUTE EXPRESS LINK CONSORTIUM, INC.’SCOMPLIANCE VERIFICATION SOFTWARE THIS END USER LICENSE AGREEMENT FOR THE CXL COMPLIANCE VERIFICATION SOFTWARE (this “Agreement“), dated as of the Effective Date (as defined below), governs all access and use of the CXL Compliance Verification Software (as defined herein), which is owned by Compute Express Link
- [Past CXL Specifications](https://computeexpresslink.org/past-cxl-specifications/) - Download an Evaluation Copy of the Past CXL® Specifications Please review the below and indicate your acceptance to receive immediate access to the archive of past Compute Express Link® Specifications. COMPUTE EXPRESS LINK CONSORTIUM, INC. EVALUATION COPY AGREEMENT – as of November 10, 2020 THIS EVALUATION COPY AGREEMENT (“Agreement”), dated as of the Effective Date
- [Past CXL Specifications Landing Page](https://computeexpresslink.org/past-cxl-specifications-landing-page/) - CXL 3.0 Specification ArchiveCXL 3.0 SpecificationCXL 3.0 Errata and Clarifications to the Compute Express Link Consortium Specification | August 2022CXL 3.0 Errata and Clarifications to the Compute Express Link Consortium Specification | December 2023CXL 2.0 Specification ArchiveCXL 2.0 SpecificationCXL 2.0 Errata and Clarifications to the Compute Express Link Consortium Specification | May 2021CXL 2.0 Engineering Change Notice:
- [Resource Library](https://computeexpresslink.org/resource-library/) - Filters: CCIX Specification Archive Demos Gen-Z Specification Archive OpenCAPI Specification Archive Presentations Technical Trainings Videos White Papers Keyword Search: Introducing the CXL 4.0 Specification Dec 4, 2025 Presentations Introducing Compute Express Link® (CXL®) 4.0: Significant Improvements in Bandwidth, Connectivity, M... Nov 18, 2025 White Papers How CXL Transforms Server Memory Infrastructure Oct 8, 2025 Presentations
- [Sitemap](https://computeexpresslink.org/sitemap/) - CXL Specification Integrators List News & Events Pressroom Member News Industry Events Resources Blog Webinars Resource Library Past CXL Specifications About Members Meet the Directors Member Companies Member Login Join CXL® Industry Liaisons CXL Specification Integrators List News & Events Pressroom Member News Industry Events Resources Blog Webinars Resource Library Past CXL Specifications About Members
- [Privacy Policies](https://computeexpresslink.org/privacy-policies/) - CXL® PRIVACY POLICY CXL® GDPR COMPLIANCE POLICY CXL® WEBSITE TERMS OF USE CXL® GDPR INFORMED CONSENT
- [CXL® GDPR INFORMED CONSENT](https://computeexpresslink.org/cxl-gdpr-informed-consent/) - COMPUTE EXPRESS LINK® CONSORTIUM, INC. GDPR INFORMED CONSENTMarch 11, 2020This Informed Consent (“Consent”) is provided by Compute Express Link® Consortium, Inc., a Delaware nonprofit corporation (“CXL®”) pursuant to the European Union’s General Data Protection Regulation (the “GDPR”). This Consent is presented to you in your status as an individual (“You” or “Data Subject” or “Your”)
- [CXL® Website Terms of Use](https://computeexpresslink.org/cxl-website-terms-of-use/) - TERMS OF USE FOR COMPUTE EXPRESS LINK® CONSORTIUM, INC.’S WEBSITEThank you for visiting the internet website at https://www.computeexpresslink.org/ (“CXL® Website”) which is owned by Compute Express Link® Consortium, Inc., a Delaware nonprofit corporation (“CXL” or “We” or “Us”). CXL provides these Terms of Use (the “Agreement”) to notify all users of CXL’s policies with regard to
- [CXL® GDPR Compliance Policy](https://computeexpresslink.org/cxl-gdpr-compliance-policy/) - COMPUTE EXPRESS LINK® CONSORTIUM, INC. GDPR COMPLIANCE POLICY (Version 1.0)Effective: March 11, 2020This GDPR Compliance Policy (also referred to as this “Compliance Policy”) represents the policy of Compute Express Link® Consortium, Inc., a Delaware nonprofit corporation (“CXL®”) regarding the treatment of all Personal Data (as defined herein) of any natural person who is a European Union (“EU”)
- [Privacy Policy](https://computeexpresslink.org/privacy-policy/) - PRIVACY POLICY OF COMPUTE EXPRESS LINK® CONSORTIUM, INC.Effective: March 11, 2020​This Privacy Policy (“Privacy Policy” or “Policy”) explains how Compute Express Link® Consortium, Inc. a Delaware nonprofit corporation (CXL®”, “We”, “Us” or “Our”) may gather, collect, record, hold, distribute, share, disclose or otherwise use any information or data about any user (“User” or “You” or
- [Press Inquiries](https://computeexpresslink.org/press-inquiries/) - Contact Us Name(Required) First Last Email(Required) Phone(Required)Add a message(Required)
- [Meet the Directors](https://computeexpresslink.org/elementor-273/) - Debendra Das Sharma CXL Board Chair Intel Corporation Read More Chris Petersen CXL Director Astera Labs, Inc. Read More Dong Wei CXL Secretary Arm Ltd. Read More Jian Chen CXL Director Alibaba (China) Co., Ltd. Read More Mahesh Wagh CXL Director Advanced Micro Devices, Inc. Read More Ramesh Sivakolundu CXL Director Cisco Systems, Inc. Read
- [Contact Us](https://computeexpresslink.org/contact-us/) - For Membership InquiriesFor Technical Questions and CommentsFor Press Inquiries
- [Sample Page](https://computeexpresslink.org/sample-page/) - This is an example page. It's different from a blog post because it will stay in one place and will show up in your site navigation (in most themes). Most people start with an About page that introduces them to potential site visitors. It might say something like this: Hi there! I'm a bike messenger

## My Templates

- [Homepage](https://computeexpresslink.org/?elementor_library=homepage) - CXL 4.0 Specification Now AvailableThe CXL 4.0 Specification increases the bandwidth from 64GTs to 128GTs, adds support for bundled ports, and enhances memory RAS features. View the Press ReleaseUpcoming Industry EventsCXL Consortium representatives regularly support presentations and technology demonstrations during industry eventsView Upcoming Events Specifications Demos Videos Contact What's New Intel: CXL Memory Modes on
- [Header](https://computeexpresslink.org/?elementor_library=elementor-header-11) - Content area
- [Error 404](https://computeexpresslink.org/?elementor_library=elementor-error-404-2029) - 404 Sorry, we can’t find the page you’re looking for.Try searching or click the button below to go back to the homepage. Search back Home
- [Events](https://computeexpresslink.org/?elementor_library=events) - Industry Events Upcoming Events CXL Mini DevCon 2026 Aug 3, 2026 Santa Clara Marriott Read More Future of Memory and Storage (FMS) 2026 Aug 4 - Aug 6, 2026 Santa Clara Convention Center, California Read More AI Infra Summit 2026 Sep 15 - Sep 17, 2026 Santa Clara, California Read More Supercomputing 2026 Nov 15
- [Single Page Default](https://computeexpresslink.org/?elementor_library=elementor-single-page-146) - Single Page Default Compute Express Link® (CXL®) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus
- [Webinars Landing PAge](https://computeexpresslink.org/?elementor_library=webinars-landing-page) - Featured Webinar Making Memories at HyperScale with CXL® October 10, 2024 Upcoming Webinars Introduction to Compute Express Link™ (CXL™) Jan 31, 2020 Past Webinars Advantages of CXL Memory Sharing for Emerging Applications Jun 4, 2025 An Overview of the CXL 3.X Specification Feb 18, 2025 Making Memories at HyperScale with CXL® Oct 10, 2024 Exploring
- [Press Room](https://computeexpresslink.org/?elementor_library=press-room) - Pressroom For media inquiries or to request a briefing, contact press@computeexpresslink.org. Filters: CXL® in the News Press Releases Keyword Search: Press Releases CXL Consortium Members – Statements of Support for CXL 4.0 Specification Nov 18, 2025 Read More CXL Consortium Releases the Compute Express Link 4.0 Specification Increasing Speed and Bandwidth Nov 18, 2025 Read More
- [Blog Archive](https://computeexpresslink.org/?elementor_library=elementor-archive-528) - Blog Archive Keyword Search: Join the CXL Ecosystem at CXL Mini DevCon 2026 Jun 30, 2026 1 min read Read More CXL® Consortium Member Spotlight: Teledyne LeCroy Jun 23, 2026 Jun 23, 2026 3 min read Read More From NVDIMM-N to CXL® Persistent Memory: Bringing Persistence to the Memory Fabric May 25, 2026 3 min
- [Meet the Directors Archive](https://computeexpresslink.org/?elementor_library=elementor-archive-397) - Meet the Directors Officers Debendra Das Sharma CXL Board Chair Intel Corporation Read More Dong Wei CXL Secretary Arm Ltd. Read More Derek Rohde CXL President and Treasurer NVIDIA Read More Board of Directors Chris Petersen CXL Director Astera Labs, Inc. Read More Jian Chen CXL Director Alibaba (China) Co., Ltd. Read More Mahesh Wagh
- [Resources Archive](https://computeexpresslink.org/?elementor_library=elementor-archive-1204) - Resources Archive < Back to Resource Library Keyword Search: Lightelligence: Photowave: Optical CXL Interconnect for Composable Data Center Architectures Nov 30, 2023 Demos Intel: CXL Memory Modes on Future Generation Intel Xeon CPUs Nov 30, 2023 Demos Xconn Technologies: CXL 2.0 Memory Pooling (Sharing) Using Xconn Switch Nov 30, 2023 Demos UniFabrix: MAXimize HPC and
- [Footer](https://computeexpresslink.org/?elementor_library=elementor-footer-59) - Content area
- [Search Results](https://computeexpresslink.org/?elementor_library=elementor-search-results-1684) - Template: Search Results Search CXL 3.0: Enabling composable systems with expanded fabric capabilities Event Oct 6, 2022 CXL 3.0: Enabling composable systems with expanded fabric capabilities Oct 19, 2022 Presentations Resource Compute Express LinkTM (CXL®): An Open Industry Standard for Composable Computing [FMS 2023 Tutorial... Jun 14, 2023 Presentations Resource Lightelligence: Photowave: Optical CXL Interconnect
- [Blog Single](https://computeexpresslink.org/?elementor_library=elementor-single-page-534) - Blog Single October 31, 2023 Introduction Computer systems have used direct attached memory modules in the form of DIMMs for decades. These modules attach directly to the host motherboard and to the CPU using a parallel bus. Expanding the number of modules a system can utilize involves adding memory controllers and pins to the CPU
- [Event Single](https://computeexpresslink.org/?elementor_library=event-single) - Event Single Jul 3, 2026 Memory Con (MemCon) March 26-27, 2024 Computer History Museum, Silicon Valley, CA CXL Consortium is excited to return as an Association Partner for MemCon 2024. Mahesh Wagh, CXL Consortium Technical Task Force Co-Chair, will participate in the following session: How to improve data movement using accelerated networks? Tuesday, March
- [Resources Single](https://computeexpresslink.org/?elementor_library=blog-single) - Resources Single Staff January 2, 2024 Demo 1: Database workload performance enhancement using CXL memory on Intel’s 5th gen Xeon (codename: Emerald Rapids) processor Demo 2: System memory TCO reduction using Flat Memory Mode on Intel’s next generation Xeon (codename: Granite Rapids) processor Facebook Twitter LinkedIn
- [Elementor Single Post #813](https://computeexpresslink.org/?elementor_library=elementor-single-post-813) - Elementor Single Post #813
- [Leader Single](https://computeexpresslink.org/?elementor_library=leader-single) - < Back to Leaders Leader Single
- [Page Header Element](https://computeexpresslink.org/?elementor_library=page-header-element) - Page Header Element
- [Meet the Directors](https://computeexpresslink.org/?elementor_library=meet-the-directors) - Debendra Das Sharma CXL Board Chair Intel Corporation Read More Chris Petersen CXL Director Astera Labs, Inc. Read More Dong Wei CXL Secretary Arm Ltd. Read More Jian Chen CXL Director Alibaba (China) Co., Ltd. Read More Mahesh Wagh CXL Director Advanced Micro Devices, Inc. Read More Ramesh Sivakolundu CXL Director Cisco Systems, Inc. Read
- [Default Kit](https://computeexpresslink.org/?elementor_library=default-kit)

## Events

- [MemCon 2024](https://computeexpresslink.org/event/memcon-2024/) - Memory Con (MemCon) March 26-27, 2024 Computer History Museum, Silicon Valley, CA CXL Consortium is excited to return as an Association Partner for MemCon 2024. Mahesh Wagh, CXL Consortium Technical Task Force Co-Chair, will participate in the following session: How to improve data movement using accelerated networks? Tuesday, March 26, 2024, 4:40 pm PT
- [AI Infra Summit 2026](https://computeexpresslink.org/event/ai-infra-summit-2026/) - The CXL Consortium looks forward to returning to the AI Infra Summit this year to highlight the benefits of CXL for AI applications. The event will gather AI infrastructure players, hosting a unique blend of systems and AI market intelligence. Use the code CXLCONSORTIUM15 for 15% off a full-access ticket. Register for the event HERE.
- [Future of Memory and Storage (FMS) 2026](https://computeexpresslink.org/event/future-of-memory-and-storage-fms-2026/) - The CXL Consortium is looking forward to returning to the Future of Memory and Storage (FMS) event at the Santa Clara Convention Center. Kiosk at the Open Standards Pavilion (Booth no. 725) Meet with CXL Consortium representatives to explore how CXL can expand your memory footprint. Contact press@computeexpresslink.org to schedule a meeting with CXL representatives.
- [Introduction to Compute Express Link™ (CXL™)](https://computeexpresslink.org/event/introduction-to-compute-express-link-cxl/) - A highly informative webinar about the CXL™ Consortium and its groundbreaking technology. Join Glenn Ward, CXL Consortium’s MWG Co-Chair and Chief of Staff, Cloud Server Infrastructure for Microsoft; Debendra Das Sharma, Intel Fellow at Intel Corporation; and Kurtis Bowman, CXL Consortium Board Member and Director, Server Architecture and Technologies at Dell EMC during this thought-provoking
- [Compute Express Link™ (CXL™): Exploring Coherent Memory and Innovative Use Cases](https://computeexpresslink.org/event/compute-express-link-cxl-exploring-coherent-memory-and-innovative-use-cases/) - CXL™ technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity.
- [Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions](https://computeexpresslink.org/event/compute-express-link-cxl-memory-challenges-and-cxl-solutions/) - Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on PCIe®), caching (CXL.cache) and memory (CXL.memory) semantics. CXL.mem allows a host processor to access memory attached to a CXL device. CXL.mem transactions are
- [Compute Express Link™ (CXL™): Introducing the Compute Express Link™ 2.0 Specification](https://computeexpresslink.org/event/compute-express-link-cxl-introducing-the-compute-express-link-2-0-specification/) - The CXL™ Consortium is proud to announce the second-generation Compute Express Link™ (CXL™). CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. This webinar will explore the new features in the CXL 2.0 specification including
- [Compute Express Link™ 2.0 Specification: Memory Pooling](https://computeexpresslink.org/event/compute-express-link-2-0-specification-memory-pooling/) - Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. In November 2020, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent
- [Compute Express Link™ (CXL™): Supporting Persistent Memory](https://computeexpresslink.org/event/compute-express-link-cxl-supporting-persistent-memory/) - Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full
- [Compute Express Link™ (CXL™) Link-level Integrity and Data Encryption (CXL IDE)](https://computeexpresslink.org/event/compute-express-link-cxl-link-level-integrity-and-data-encryption-cxl-ide/) - Security is a key cornerstone for any technology to be successful and CXL is making great strides in security by working collaboratively with other industry-standard bodies such as PCI-SIG and DMTF to ensure a seamless user experience with the best security mechanisms. CXL 2.0 enhances the security mechanism from CXL 1.1 and 1.0 by adding
- [An Overview of the Compute Express Link™ (CXL™) 2.0 ECN](https://computeexpresslink.org/event/an-overview-of-the-compute-express-link-cxl-2-0-ecn/) - In November 2020, the CXL Consortium released the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility. Based on member feedback, CXL 2.0 ECNs made significant improvements to the specifications in the areas of device management, RAS, Security,
- [Introduction to the Compute Express Link™ (CXL™) Fabric Manager](https://computeexpresslink.org/event/introduction-to-the-compute-express-link-cxl-fabric-manager/) - Compute Express Link™ (CXL™) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers and smart I/O devices. The CXL 2.0 specification introduces a standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch
- [CXL 1.1 vs. CXL 2.0 – What’s the difference?](https://computeexpresslink.org/event/cxl-1-1-vs-cxl-2-0-whats-the-difference/) - Compute Express Link™ (CXL™) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 1.1 specification introduced and defined the CXL I/O protocol, memory protocol, and coherency interface. The CXL 2.0 specification adds support for switching
- [CXL 3.0: Enabling composable systems with expanded fabric capabilities](https://computeexpresslink.org/event/cxl-3-0-enabling-composable-systems-with-expanded-fabric-capabilities/) - In August 2022, CXL Consortium released the CXL 3.0 specification. CXL 3.0 expands on previous technology generations to increase scalability and optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. It also doubles the data rate to 64 GT/s with no added latency
- [A look into the CXL device ecosystem and the evolution of CXL use cases](https://computeexpresslink.org/event/a-look-into-the-cxl-device-ecosystem-and-the-evolution-of-cxl-use-cases/) - Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion, and accelerators. CXL enables a high-speed, efficient interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions. At Supercomputing 2022 (SC’22), CXL Consortium members showcased CXL technology demonstrations on memory solutions, IP,
- [CXL Consortium Compliance Program Overview: Integrators List & Feature Testing](https://computeexpresslink.org/event/cxl-consortium-compliance-program-overview-integrators-list-feature-testing/) - CXL Consortium member companies are developing a wide range of products and solutions including CXL memory solutions, IP, compliance testing, fabric implementations, switches, and software solutions. Compliance and interoperability between these products are essential to creating a technology standard that will be successfully deployed in commercially available systems across multiple vendors. This webinar will highlight
- [Increasing Memory Utilization and Reducing Total Memory Cost Using CXL](https://computeexpresslink.org/event/increasing-memory-utilization-and-reducing-total-memory-cost-using-cxl/) - CXL’s advanced memory expansion and fabric management capabilities can be used to increase system scalability and flexibility across multiple compute domains, enabling resource sharing for higher performance, reduced software stack complexity, and lower overall datacenter memory cost. The fabric enhancements and memory expansion features included in CXL 3.0 deliver new levels of composability required by
- [Introducing the CXL 3.1 Specification](https://computeexpresslink.org/event/introducing-the-cxl-3-1-specification-2/) - The CXL 3.1 Specification introduces enhancements to fabric capability and manager API definition for PBR switch, inter-host communication using Global Integrated Memory (GIM), Trusted-Execution-Environment Security Protocol (TSP), and memory expander improvements. These enhancements will enable composable and disaggregated systems to keep up with the demand for high-performance computational workloads. This webinar introduced the CXL 3.1
- [Breaking Memory Barriers: CXL's Game-Changing Impact on AI/ML](https://computeexpresslink.org/event/breaking-memory-barriers-cxls-game-changing-impact-on-ai-ml-2/) - View this webinar recording to explore Compute Express Link (CXL) technology and its immediate impact on AI and ML applications. You'll discover how CXL is revolutionizing data center performance and efficiency. During the webinar, we explored the current state of the CXL ecosystem, including the latest advancements in both hardware and software. Learn about the
- [Exploring CXL® Use Cases and Implementations](https://computeexpresslink.org/event/exploring-cxl-use-cases-and-implementations/) - CXL is an open coherent interconnect standard that enables heterogeneous computing, increases memory capacity and bandwidth, and optimizes performance for current workloads and emerging applications. CXL Consortium members are offering products based on the CXL 1.1 and 2.0 specifications and developing products based on the CXL 3.x specification. Join CXL Consortium member companies Astera Labs,
- [Making Memories at HyperScale with CXL®](https://computeexpresslink.org/event/making-memories-at-hyperscale-with-cxl/) - Presenters: Brian Morris, Google, and Prakash Chauhan, Meta Date and Time: October 10 at 8:00 am PT CXL® (Compute Express Link®) enables the addition of a new tier of memory to the memory hierarchy using type-3 devices. There are many first-generation CXL memory expansion devices in the market that will allow this capability. However, due
- [STAC Summit - New York](https://computeexpresslink.org/event/stac-summit-new-york/) - The CXL Consortium is looking forward to presenting at the STAC Summit - New York event to highlight the benefits of CXL for trading and analytics. Presentation title: Memory Is the New Bottleneck, And It’s Now Software Defined Date and time: May 20 at 9:35 am ET Speaker: Luis Ancajas, Director of CXL Products Management
- [Supercomputing 2026](https://computeexpresslink.org/event/supercomputing-2026/) - The CXL Consortium is returning to Supercomputing 2026 (SC26) to showcase the benefits of CXL for AI and HPC applications. CXL Pavilion (Booth no. 1218) Visit the CXL Pavilion to view live CXL technology demonstrations. Stay tuned for updates!
- [CXL Mini DevCon 2026](https://computeexpresslink.org/event/cxl-mini-devcon-2026/) - The CXL® Consortium is looking forward to hosting the 2026 CXL Mini-DevCon on August 3, 2026, at the Santa Clara Marriott in Santa Clara, California. The CXL Mini-DevCon is a unique opportunity for Consortium members to learn directly from CXL technology experts. During the event, you will be able to participate in CXL technical training
- [Vertical Optimization of the CXL Stack](https://computeexpresslink.org/event/overcoming-cxl-limitations-enabling-cxl-hardware-and-software-as-vertical-optimization-technologies/) - Compute Express Link (CXL) has emerged as a critical technology for modern server systems, offering the ability to expand memory bandwidth and capacity while significantly reducing Total Cost of Ownership (TCO) by minimizing stranded memory. However, widespread adoption faces three primary challenges: higher latency compared to traditional DIMMs, insufficient bandwidth for data-intensive AI applications, and
- [The Xcelerated Compute Show](https://computeexpresslink.org/event/the-xcelerated-compute-show/) - The Xcelerated Compute Show brings together 550+ leaders from across hyperscale, neocloud, enterprise, and the wider ecosystem. The CXL Consortium is thrilled to be a Media & Industry partner of the Xcelerated Compute Show taking place from March 23-24 at the Marriott Marquis, Times Square, NYC. Panel: State of Storage – How data storage will
- [Introducing the CXL 4.0 Specification](https://computeexpresslink.org/event/introducing-the-cxl-4-0-specification/) - The CXL Consortium released the CXL 4.0 Specification to meet the increasing demands of emerging workloads placed on today’s data centers. CXL 4.0 builds on previous generations, doubling the bandwidth from 64 GTs to 128GTs, adds support for bundled ports, and enhances memory RAS features. Join this webinar to explore the new features in the
- [Supercomputing 2025](https://computeexpresslink.org/event/supercomputing-2025/) - The CXL Consortium is looking forward to returning to Supercomputing 2025 (SC'25) to highlight the benefits of CXL technology for AI and HPC applications. Birds of a Feather Presentation: How to Leverage CXL Memory Pooling and Sharing for AI & HPC workloads Date and time: Tuesday, November 18, 12:15 - 1:15 pm PT Moderator: Anil
- [OCP Global Summit](https://computeexpresslink.org/event/ocp-global-summit-2/) - The CXL Consortium looks forward to presenting at the 2025 OCP Global Summit event at the San Jose Convention Center from October 13 to 16, 2025. CXL Presentation on Wednesday, October 15 Title: Large CXL Memory Expansion Systems and Workloads Date and time: October 15 at 12:30 - 12:45 pm PT Location: SJCC - Concourse
- [How CXL Transforms Server Memory Infrastructure](https://computeexpresslink.org/event/how-cxl-transforms-server-memory-infrastructure/) - CXL technology allows both coherent shared and dedicated pooled memory to serve different purposes – enabling a composable data center architecture and providing a cost-efficient solution to expand memory, while improving overall performance for memory-intensive applications like In-Memory Database, HPC, and AI/ML. During the webinar, attendees will explore the benefits of CXL memory pooling and
- [AI Infra Summit 2025](https://computeexpresslink.org/event/ai-infra-summit-2025/) - The CXL Consortium looks forward to participating in the AI Infra Summit event to promote the benefits of CXL technology for AI applications. The AI Infra Summit is the world’s largest and most established AI conference that focuses on the infrastructure layer of AI & Machine Learning. Originating as the AI Hardware Summit back in
- [SDC 2025](https://computeexpresslink.org/event/sdc-2025/) - The CXL Consortium is looking forward to presenting at the SNIA Developer Conference (SDC) to highlight the advantages of CXL for cloud and computational storage. Join our presentation: Advantages of CXL Memory Pooling and Tiering Monday, September 15, from 12:00 - 12:25 pm PT Presenter: Anil Godbole, CXL MWG Chair
- [Future Memory Storage (FMS) 2025](https://computeexpresslink.org/event/fms-2025/) - The CXL Consortium looks forward to participating in the Future of Memory and Storage (FMS) event at the Santa Clara Convention Center from August 5-7, 2025. CXL Kiosk at the Open Standards Pavilion (Booth no. 725) Explore how CXL can expand your memory footprint by visiting our representatives at our kiosk. View the CXL Video
- [Advantages of CXL Memory Sharing for Emerging Applications](https://computeexpresslink.org/event/advantages-of-cxl-memory-sharing-for-emerging-applications/) - This webinar will explore the benefits of CXL memory sharing and how CXL shared memory will improve performance for Big Data Analytics, AI, and more. CXL Consortium members Astera Labs, Micron Technology, UnfabriX, and XConn Technologies will share real-world usage models of CXL memory sharing for finance, AI, and database applications. Watch the webinar HERE.
- [CXL DevCon 2025](https://computeexpresslink.org/event/cxl-devcon-2025/) - Thank you for supporting the 2025 Compute Express Link® (CXL®) DevCon! CXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. During the event, attendees participated in CXL technical training, viewed available products and technology demonstrations, and networked with industry peers. Learn more about this year's event HERE. If
- [An Overview of the CXL 3.X Specification](https://computeexpresslink.org/event/an-overview-of-the-cxl-3-x-specification/) - Date and Time: February 18 at 9:00 am PT Presenter: Mahesh Natu, Intel The CXL® 3.X specification was introduced to support AI and ML workloads for cloud and on-premise applications, providing advanced switching and fabrics capabilities for CXL devices, efficient peer-to-peer communications, and resource sharing across compute domains. CXL 3.2 builds upon these advancements for
- [Breaking Memory Barriers: CXL's Game-Changing Impact on AI/ML](https://computeexpresslink.org/event/breaking-memory-barriers-cxls-game-changing-impact-on-ai-ml/) - Presenter: Steve Scargall, MemVerge Date and Time: December 19 at 9:00 am PST Join us for a live webinar on Compute Express Link (CXL) technology and its immediate impact on AI and ML applications. You'll discover how CXL is revolutionizing data center performance and efficiency. We'll explore the current state of the CXL ecosystem, including
- [Supercomputing 2024](https://computeexpresslink.org/event/supercomputing-2023/) - CXL Consortium representatives will be providing an update from the Consortium and highlighting the benefits of CXL technology for AI and HPC applications during the following session: Exhibitor Forum presentation: CXL Consortium Progress Report: Available CXL Devices in the Market Date and time: Tuesday, November 19, 10:30 - 11:00 am ET Speakers: Kurtis Bowman (AMD)
- [Future Memory Storage (FMS) 2024](https://computeexpresslink.org/event/future-memory-storage-fms-2024/) - The CXL Consortium is looking forward to presenting at the Future of Memory and Storage (FMS), from August 6 - 8, 2024, at the Santa Clara Convention Center. CXL Consortium representatives and our members will be presenting the following sessions: Tuesday, August 6, 2024, 8:30 - 9:30 AM PT: How to boost memory capacity and
- [CXL DevCon 2024](https://computeexpresslink.org/event/cxl-devcon-2024/) - CXL Consortium Developers Conference (DevCon) 2024 April 30 – May 1, 2024 Santa Clara, California The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1, 2024, in Santa Clara, California! CXL DevCon is a unique opportunity for our Members to learn directly from CXL
- [2024 SNIA Compute, Memory, and Storage (CMS) Summit](https://computeexpresslink.org/event/2024-snia-compute-memory-and-storage-cms-summit/) - CXL Consortium is excited to present at the SNIA CMS Summit. The Summit brings together the leading experts on the current and future topics in the compute, memory, and storage ecosystem, including AI, cloud, CXL, future trends, sustainability, and storage networking in an interactive setting. Presentation topic: Increasing AI and HPC Application Performance with CXL
- [ISC HPC 2024](https://computeexpresslink.org/event/isc-hpc-2024/) - The CXL Consortium is excited to present a Birds of a Feather presentation at ISC HPC 2024. Increasing memory utilization and reducing total memory cost using CXL® Monday, May 13, 2024, 5:40 - 6:40 pm CET Location: Hall F – 2nd Floor Presenters: John Ihnotic (GigaIO), Borja Comendeiro (Liqid), Klas Moreau (ZeroPoint Technologies)
- [2024 Virtual OFA Workshop](https://computeexpresslink.org/event/2024-virtual-ofa-workshop/) - The CXL Consortium is looking forward to presenting at the annual OFA Workshop. The annual workshop fosters collaboration between those who develop fabrics, deploy fabrics, and create applications that rely on fabrics. The event enables fabric developers and users to discuss emerging fabric technologies, collaborate on future industry requirements, and address problems that exist today.
- [OCP Global Summit](https://computeexpresslink.org/event/ocp-global-summit/) - Mahesh Wagh, CXL Consortium Technical Task Force Co-Chair, will explore features in the CXL 3.0 specification during the CXL Forum, scheduled on Thursday, October 19. ​ ​ Stay tuned for more information.

## Leadership

- [Moinuddin Qureshi](https://computeexpresslink.org/leader/moinuddin-qureshi/) - Moinuddin Qureshi is a Principal Engineer in Google Cloud, looking at architecting memory-efficient servers. He has over two decades of experience in memory system design, including conducting research in industry, as a research scientist at IBM T. J. Watson and in academia, as a tenured Professor of Computer Science at the Georgia Institute of Technology.
- [Debendra Das Sharma](https://computeexpresslink.org/leader/debendra-das-sharma/) - Dr. Debendra Das Sharma is an Intel Senior Fellow and Chief I/O Architect, Data Center Group, at Intel Corporation. He is a member of NAE, Fellow of IEEE, and Fellow of International Academy of AI Sciences (AAIS). He is a leading expert on I/O subsystem and interface architecture. He delivers Intel-wide critical interconnect technologies in
- [Dong Wei](https://computeexpresslink.org/leader/dong-wei/) - Dong Wei is an Arm Fellow and Lead Standards Architect of the Architecture and Technology Group in Arm Limited. Dong joined Arm in 2016. He leads the system architecture for the Arm-based server, DPU , PC and Windows IoT systems, covering industry standards such as PCI Express, Trusted Computing, CXL, UEFI, ACPI, DMTF (Redfish, PMCI
- [Siamak Tavallaei](https://computeexpresslink.org/leader/siamak-tavallaei/) - Mr. Tavallaei brings a distinguished record of leadership, technical innovation, and strategic engagement that has significantly advanced the mission and global impact of CXL Consortium since its inception. He has served the Consortium as President, Board Director, Independent Advisor to the Board, founding Co-Chair of the Technical Task Force (TTF), and active member of the
- [Ramesh Sivakolundu](https://computeexpresslink.org/leader/ramesh-sivakolundu/) - Bio & photo coming soon.
- [Mahesh Wagh](https://computeexpresslink.org/leader/mahesh-wagh/) - Bio & photo coming soon.
- [Kevin Depew](https://computeexpresslink.org/leader/kevin-depew/) - Bio coming soon.
- [Shawn Dube](https://computeexpresslink.org/leader/shawn-dube/) - Shawn is completing his third decade within the computer systems industry. His past work has focused on enterprise and scale-out server systems. He served as chief architect for multiple modular/blade compute systems with an emphasis on composability. Over the last decade Shawn has focused on pathfinding of new technologies and their introduction into Dell’s server
- [Derek Rohde](https://computeexpresslink.org/leader/derek-rohde/) - Derek Rohde is a Principal Engineer at NVIDIA where he works on CXL and PCIe architecture. He has over 25 years of experience working on various I/O and networking technologies. His past standards experience includes serving as vice-chairman of the TDL workgroup in the CCIX Consortium and participating in the IEEE 802.1 Data Center Bridging
- [Chris Petersen](https://computeexpresslink.org/leader/chris-petersen/) - Chris Petersen is a Fellow of Technology and Ecosystems and is responsible for pathfinding for the Astera Labs’ product roadmap and driving the ecosystem enablement for all new products. Chris has more than 20 years of in-depth experience in architecting AI and cloud servers, memory, storage, accelerators, fabrics, and datacenter solutions. Prior to Astera Labs, Chris
- [Thomas Won Ha Choi](https://computeexpresslink.org/leader/thomas-won-ha-choi/) - Thomas Won Ha Choi is a Distinguished Engineer and Memory Systems Architect at SK hynix, specializing in memory standardization and pathfinding of next-generation memory products. Thomas is involved in various memory standardization projects in CXL Consortium and JEDEC, and he is experienced with standardization of next-generation memory interconnect such as CXL, CCIX, Gen-Z and JEDEC
- [Glenn Ward](https://computeexpresslink.org/leader/glenn-ward/) - Glenn Ward is a Senior Director of Technology Development in the Azure division at Microsoft. Glenn and his team focus on driving development of new technologies for consumption in Microsoft Azure, and Microsoft Cloud services. Prior to joining Microsoft, Glenn earned his master’s degree at the Kellogg GSM, Northwestern University. Before Kellogg, Glenn was a
- [Prakash Chauhan](https://computeexpresslink.org/leader/prakash-chauhan/) - Prakash Chauhan is a Hardware Technologist at Meta since 2020, with over 25 years of industry experience. Prakash has a broad background in architecture and design of hardware systems, and deploying them at hyperscale, to deliver improved generational performance improvements at optimal cost. Prakash has been closely involved with the CXL consortium since its inception.
- [Alex Umansky](https://computeexpresslink.org/leader/alex-umansky/) - Bio Coming
- [Jian Chen](https://computeexpresslink.org/leader/jian-chen/) - Dr. Jian Chen is the director of engineering in Alibaba Cloud where he leads the initiatives in the Infrastructure team to bring core competence in the area of general purpose computing. The scope of his work ranges from CPU customization for next-gen servers, workload characterization and performance analysis, high speed interconnection technologies, to disaggregated server

## Members

- [Sandisk Technologies, Inc.](https://computeexpresslink.org/member/western-digital/)
- [HPE](https://computeexpresslink.org/member/hpe/)
- [Numascale](https://computeexpresslink.org/member/numascale/)
- [JumpTrading](https://computeexpresslink.org/member/jumptrading/)
- [Ericsson](https://computeexpresslink.org/member/ericsson/)
- [Netlist Inc.](https://computeexpresslink.org/member/netlist-inc/)
- [Intel](https://computeexpresslink.org/member/intel/)
- [NVIDIA](https://computeexpresslink.org/member/nvidia/)
- [Huawei](https://computeexpresslink.org/member/huawei/)
- [Seagate](https://computeexpresslink.org/member/seagate/)
- [ZeroPoint Technology Inc.](https://computeexpresslink.org/member/zeropoint-technology-inc/)
- [Wuxi Stars Mico System Technologies Co., LTD](https://computeexpresslink.org/member/wuxi-stars-mico-system-technologies-co-ltd/)
- [Xi'an UnilC](https://computeexpresslink.org/member/xian-unilc/)
- [XConn Tech](https://computeexpresslink.org/member/xconn-tech/)
- [Viavi Solutions](https://computeexpresslink.org/member/viavi-solutions/)
- [UniFabriX](https://computeexpresslink.org/member/unifabrix/)
- [TrueChip Solutions](https://computeexpresslink.org/member/truechip-solutions/)
- [Teledyne Lecroy](https://computeexpresslink.org/member/teledyne-lecroy/)
- [TE Connectivity](https://computeexpresslink.org/member/te-connectivity/)
- [Synopsys](https://computeexpresslink.org/member/synopsys/)
- [Shenzhen Tencent](https://computeexpresslink.org/member/shenzhen-tencent/)
- [Scaleflux](https://computeexpresslink.org/member/scaleflux/)
- [Rambus](https://computeexpresslink.org/member/rambus-2/)
- [Qualcomm](https://computeexpresslink.org/member/qualcomm/)
- [Phison Electronics Corp.](https://computeexpresslink.org/member/phison-electronics-corp/)
- [Parade Tech](https://computeexpresslink.org/member/parade-tech/)
- [Panmnesia](https://computeexpresslink.org/member/panmnesia/)
- [Oracle Corporation](https://computeexpresslink.org/member/oracle-corporation/)
- [Nippon Telegraph and Telephone Corp](https://computeexpresslink.org/member/nippon-telegraph-and-telephone-corp/)
- [Nanning technologies](https://computeexpresslink.org/member/nanning-technologies/)
- [Montage Technology](https://computeexpresslink.org/member/montage-technology/)
- [Microchip](https://computeexpresslink.org/member/microchip/)
- [Maxlinear](https://computeexpresslink.org/member/maxlinear/)
- [Marvell](https://computeexpresslink.org/member/marvell/)
- [Liqid](https://computeexpresslink.org/member/liqid/)
- [Lenovo](https://computeexpresslink.org/member/lenovo/)
- [Kioxia](https://computeexpresslink.org/member/kioxia/)
- [Keysight Technologies](https://computeexpresslink.org/member/keysight-technologies/)
- [Jaguar Microsystems](https://computeexpresslink.org/member/jaguar-microsystems/)
- [H3C](https://computeexpresslink.org/member/h3c/)
- [Fujitsu](https://computeexpresslink.org/member/fujitsu/)
- [Ellisys](https://computeexpresslink.org/member/ellisys/)
- [Cadence Design Systems](https://computeexpresslink.org/member/cadence-design-systems/)
- [Samsung](https://computeexpresslink.org/member/samsung/)
- [Microsoft](https://computeexpresslink.org/member/microsoft/)
- [Meta](https://computeexpresslink.org/member/meta/)
- [Google](https://computeexpresslink.org/member/google/)
- [Zettai LLC](https://computeexpresslink.org/member/zettai-llc/)
- [SiMa Technologies](https://computeexpresslink.org/member/sima-technologies/)
- [InnoGrit Corporation](https://computeexpresslink.org/member/innogrit-corporation/)
- [I Machines, Inc](https://computeexpresslink.org/member/i-machines-inc/)
- [Axiado Corporation](https://computeexpresslink.org/member/axiado-corporation/)
- [Samtec Inc.](https://computeexpresslink.org/member/samtec-inc/)
- [SMART Modular Technologies](https://computeexpresslink.org/member/smart-modular-technologies/)
- [Anritsu Corporation](https://computeexpresslink.org/member/anritsu-corporation-2/)
- [Foxlink Interconnect Inc](https://computeexpresslink.org/member/foxlink-interconnect-inc/)
- [Eliyan](https://computeexpresslink.org/member/advantest/)
- [AkroStar Technology Co.,Ltd.](https://computeexpresslink.org/member/akrostar-technology-co-ltd/)
- [SunRise Memory Corp.](https://computeexpresslink.org/member/sunrise-memory-corp/)
- [Silicon45 Corp.](https://computeexpresslink.org/member/silicon45-corp/)
- [Foxconn Interconnect Technology](https://computeexpresslink.org/member/foxconn-interconnect-technology/)
- [StarFive International Pte Ltd](https://computeexpresslink.org/member/starfive-international-pte-ltd/)
- [MangoBoost](https://computeexpresslink.org/member/mangoboost/)
- [Lightelligence](https://computeexpresslink.org/member/https-www-lightelligence-ai/)
- [Silicon Innovation Technologies Co., Ltd.](https://computeexpresslink.org/member/silicon-innovation-technologies-co-ltd/)
- [Sonid Ronotics. Co., Ltd.](https://computeexpresslink.org/member/sonid-ronotics-co-ltd/)
- [SkyeChip](https://computeexpresslink.org/member/skyechip/)
- [Silicom Ltd.](https://computeexpresslink.org/member/silicom-ltd/)
- [Signature IP Corporation](https://computeexpresslink.org/member/signature-ip-corporation/)
- [Siemens Industry Software Inc.](https://computeexpresslink.org/member/siemens-industry-software-inc/)
- [Shanghai Zijing Xinjie Intelligent Technology Co., Ltd.](https://computeexpresslink.org/member/shanghai-zijing-xinjie-intelligent-technology-co-ltd/)
- [Quantum Core Cloud (Beijing) Microelectronics Technology Co., Ltd.](https://computeexpresslink.org/member/quantum-core-cloud-beijing-microelectronics-technology-co-ltd/)
- [Pegatron Corporation](https://computeexpresslink.org/member/pegatron-corporation/)
- [MindShare, Inc.](https://computeexpresslink.org/member/mindshare-inc/)
- [Jackrabbit Founders LLC](https://computeexpresslink.org/member/jackrabbit-founders-llc/)
- [Iron Labs LTD.](https://computeexpresslink.org/member/iron-labs-ltd/)
- [Hitachi Vantara, Ltd.](https://computeexpresslink.org/member/hitachi-ltd/)
- [ATTO Technology, Inc](https://computeexpresslink.org/member/atto-technology-inc/)
- [Anapass, Inc](https://computeexpresslink.org/member/anapass-inc/)
- [Arteris](https://computeexpresslink.org/member/arteris/)
- [Astera Labs](https://computeexpresslink.org/member/astera-labs/)
- [SK Hynix](https://computeexpresslink.org/member/sk-hynix/)
- [Rambus](https://computeexpresslink.org/member/rambus/)
- [IBM](https://computeexpresslink.org/member/ibm/)
- [IEIT Systems Co., Ltd.](https://computeexpresslink.org/member/ieit-systems-co-ltd/)
- [TechBridge BCA Consulting](https://computeexpresslink.org/member/techbridge-bca-consulting/)
- [XCENA Inc.](https://computeexpresslink.org/member/metisx/)
- [Honda Motor Co., Ltd.](https://computeexpresslink.org/member/honda-motor-co-ltd/)
- [Micron Technologies](https://computeexpresslink.org/member/micron-technologies/)
- [Servants International Corporation](https://computeexpresslink.org/member/servants-international-corporation/)
- [Primemas Inc.](https://computeexpresslink.org/member/primemas-inc/)
- [Cascade X, Inc.](https://computeexpresslink.org/member/cascade-x-inc/)
- [Cyber Together](https://computeexpresslink.org/member/cyber-together/)
- [United Micro Technology (Shenzhen) Co., Ltd.](https://computeexpresslink.org/member/united-micro-technology-shenzhen-co-ltd/)
- [Scalemem](https://computeexpresslink.org/member/scale/)
- [Lecarc Co. Ltd](https://computeexpresslink.org/member/lecarc-co-ltd/)
- [Allion](https://computeexpresslink.org/member/allion/)
- [Patriot Memory Inc.](https://computeexpresslink.org/member/patriot-memory-inc/)
- [Sony Interactive Entertainment, LLC](https://computeexpresslink.org/member/sony-semiconductor/)
- [Analogue Insight](https://computeexpresslink.org/member/analogue-insight/)
- [Surge Intelligence](https://computeexpresslink.org/member/surge-intelligence/)
- [ADATA Technology Co., Ltd](https://computeexpresslink.org/member/adata-technology-co-ltd/)
- [ZTE Corporation](https://computeexpresslink.org/member/zte-corporation/)
- [ExpectedIT GmbH](https://computeexpresslink.org/member/expectedit-gmbh/)
- [Aclectic Systems Inc.](https://computeexpresslink.org/member/aclectic-systems-inc/)
- [AP Memory Corp, USA](https://computeexpresslink.org/member/ap-memory-corp-usa/)
- [Barcelona Supercomputing Center](https://computeexpresslink.org/member/barcelona-supercomputing-center-2/)
- [Agiliad Technologies Private Limited](https://computeexpresslink.org/member/agiliad-technologies-private-limited/)
- [ELSA Japan Inc.](https://computeexpresslink.org/member/elsa-japan-inc/)
- [BIWIN Storage Technology Co., Ltd.](https://computeexpresslink.org/member/biwin-storage-technology-co-ltd/)
- [Shenzhen Longsys Electronics Co., Ltd.](https://computeexpresslink.org/member/shenzhen-longsys-electronics-co-ltd/)
- [JPC Connectivity](https://computeexpresslink.org/member/jpc-connectivity/)
- [VA Linux Systems Japan K.K.](https://computeexpresslink.org/member/va-linux-systems-japan-k-k/)
- [SmartDV Technologies India Private Limited](https://computeexpresslink.org/member/smartdv-technologies-india-private-limited/)
- [ARM](https://computeexpresslink.org/member/arm/)
- [ZT Systems](https://computeexpresslink.org/member/zt-systems/)
- [ZhangZhou DingDangChengZi Computer](https://computeexpresslink.org/member/zhangzhou-dingdangchengzi-computer/)
- [YEESTOR Microelectronics Co., Ltd.](https://computeexpresslink.org/member/yeestor-microelectronics-co-ltd/)
- [Yangtze Memory Technologies Co., Ltd.](https://computeexpresslink.org/member/yangtze-memory-technologies-co-ltd/)
- [Yangtze Advanced Memory Industrial Innovation Center Co., Ltd](https://computeexpresslink.org/member/yangtze-advanced-memory-industrial-innovation-center-co-ltd/)
- [Xsight Labs Ltd](https://computeexpresslink.org/member/xsight-labs-ltd/)
- [Wolley (Taiwan) Ltd.](https://computeexpresslink.org/member/wolley-taiwan-ltd/)
- [Wiwynn Corporation](https://computeexpresslink.org/member/wiwynn-corporation/)
- [Wisewave (Zhuhai) Technology Co., Ltd](https://computeexpresslink.org/member/wisewave-zhuhai-technology-co-ltd/)
- [Wilder Technologies](https://computeexpresslink.org/member/wilder-technologies/)
- [Webdock.io](https://computeexpresslink.org/member/webdock-io/)
- [Visionbrewers](https://computeexpresslink.org/member/visionbrewers/)
- [Viking Technology](https://computeexpresslink.org/member/viking-technology/)
- [VeriSilicon Inc.](https://computeexpresslink.org/member/verisilicon-inc/)
- [VeriFast Technologies, Inc.](https://computeexpresslink.org/member/verifast-technologies-inc/)
- [Vaaluka Solutions Private Limited](https://computeexpresslink.org/member/vaaluka-solutions-private-limited/)
- [UW-Madison](https://computeexpresslink.org/member/uw-madison/)
- [Unigen Corporation](https://computeexpresslink.org/member/unigen-corporation/)
- [ULINK Technology](https://computeexpresslink.org/member/ulink-technology/)
- [Triad National Security, LLC](https://computeexpresslink.org/member/triad-national-security-llc/)
- [Texas Instruments](https://computeexpresslink.org/member/texas-instruments/)
- [Teradyne Inc.](https://computeexpresslink.org/member/teradyne-inc/)
- [Tactical Computing Laboratories](https://computeexpresslink.org/member/tactical-computing-laboratories/)
- [Tachyum Inc.](https://computeexpresslink.org/member/tachyum-inc/)
- [Sysgear Inc.](https://computeexpresslink.org/member/sysgear-inc/)
- [Stream Computing](https://computeexpresslink.org/member/stream-computing/)
- [Stratus Technologies, Inc.](https://computeexpresslink.org/member/stratus-technologies-inc/)
- [Spirent Communications](https://computeexpresslink.org/member/spirent-communications/)
- [Socionext Inc.](https://computeexpresslink.org/member/socionext-inc/)
- [Silverdraft Supercomputing](https://computeexpresslink.org/member/silverdraft-supercomputing/)
- [Silicon Motion, Inc.](https://computeexpresslink.org/member/silicon-motion-inc/)
- [Silicon Integrated Systems Corp.](https://computeexpresslink.org/member/silicon-integrated-systems-corp/)
- [Silex Insight](https://computeexpresslink.org/member/silex-insight/)
- [Silarra Technologies Pvt Ltd](https://computeexpresslink.org/member/silarra-technologies-pvt-ltd/)
- [Shenzhen Union Memory Information System Co., Ltd](https://computeexpresslink.org/member/shenzhen-union-memory-information-system-co-ltd/)
- [Shanghai Zhaoxin Semiconductor Co., Ltd.](https://computeexpresslink.org/member/shanghai-zhaoxin-semiconductor-co-ltd/)
- [Shanghai ThinkForce Electronics Co. Ltd](https://computeexpresslink.org/member/shanghai-thinkforce-electronics-co-ltd/)
- [Shanghai Enflame Technology Co. Ltd](https://computeexpresslink.org/member/shanghai-enflame-technology-co-ltd/)
- [Sevya LLC](https://computeexpresslink.org/member/sevya-llc/)
- [SerialTek](https://computeexpresslink.org/member/serialtek/)
- [ScaleMP Inc.](https://computeexpresslink.org/member/scalemp-inc/)
- [Sambanova Systems](https://computeexpresslink.org/member/sambanova-systems/)
- [Sahil Semiconductor Inc](https://computeexpresslink.org/member/sahil-semiconductor-inc/)
- [Rockwell Automation](https://computeexpresslink.org/member/rockwell-automation/)
- [Giga Computing Technology Co., Ltd.](https://computeexpresslink.org/member/giga-computing-technology-co-ltd/)
- [Groq Inc.](https://computeexpresslink.org/member/groq-inc/)
- [Grovf Inc.](https://computeexpresslink.org/member/grovf-inc/)
- [H3 Platform Inc.](https://computeexpresslink.org/member/h3-platform-inc/)
- [HS Devices d.o.o. Nis](https://computeexpresslink.org/member/hs-devices-d-o-o-nis/)
- [HuaQin Technology Co., Ltd](https://computeexpresslink.org/member/huaqin-technology-co-ltd/)
- [Iluvatar CoreX Inc.](https://computeexpresslink.org/member/iluvatar-corex-inc/)
- [imec vzw](https://computeexpresslink.org/member/imec-vzw/)
- [InAccel](https://computeexpresslink.org/member/inaccel/)
- [InfiniLink](https://computeexpresslink.org/member/infinilink/)
- [Innodisk Corporation](https://computeexpresslink.org/member/innodisk-corporation/)
- [Intelliprop, Inc](https://computeexpresslink.org/member/intelliprop-inc/)
- [Insyde Software, Inc.](https://computeexpresslink.org/member/insyde-software-inc/)
- [Inventec Corporation](https://computeexpresslink.org/member/inventec-corporation/)
- [Jabil](https://computeexpresslink.org/member/jabil/)
- [Kontron](https://computeexpresslink.org/member/kontron/)
- [Level IT](https://computeexpresslink.org/member/level-it/)
- [Linode](https://computeexpresslink.org/member/linode/)
- [Liquid-Markets GmbH](https://computeexpresslink.org/member/liquid-markets-gmbh/)
- [Lotes Co., Ltd.](https://computeexpresslink.org/member/lotes-co-ltd/)
- [Lyle Technologies LLP](https://computeexpresslink.org/member/lyle-technologies-llp/)
- [Macom Technology Solutions](https://computeexpresslink.org/member/macom-technology-solutions/)
- [Mangata Networks](https://computeexpresslink.org/member/mangata-networks/)
- [Mempath Consulting LLC](https://computeexpresslink.org/member/mempath-consulting-llc/)
- [Memsule, Inc.](https://computeexpresslink.org/member/memsule-inc/)
- [MetaX Integrated Circuits (Shanghai) Co., Ltd](https://computeexpresslink.org/member/metax-integrated-circuits-shanghai-co-ltd/)
- [MicroIP Inc.](https://computeexpresslink.org/member/microip-inc/)
- [Micro-Star Int’l Co., Ltd.](https://computeexpresslink.org/member/micro-star-intl-co-ltd/)
- [MiTAC Computing Technology Corp.](https://computeexpresslink.org/member/mitac-computing-technology-corp/)
- [Molex LLC](https://computeexpresslink.org/member/molex-llc/)
- [Mossbit Technologies](https://computeexpresslink.org/member/mossbit-technologies/)
- [Nanya Technology Corporation](https://computeexpresslink.org/member/nanya-technology-corporation/)
- [NEC Corporation](https://computeexpresslink.org/member/nec-corporation/)
- [Neuchips Inc](https://computeexpresslink.org/member/neuchips-inc/)
- [Neuron IP Inc.](https://computeexpresslink.org/member/neuron-ip-inc/)
- [NGD Systems, Inc.](https://computeexpresslink.org/member/ngd-systems-inc/)
- [Norel Systems LTD](https://computeexpresslink.org/member/norel-systems-ltd/)
- [ONE Semiconductor](https://computeexpresslink.org/member/one-semiconductor/)
- [One Stop Systems, Inc.](https://computeexpresslink.org/member/one-stop-systems-inc/)
- [OPENEDGES Technology, Inc.](https://computeexpresslink.org/member/openedges-technology-inc/)
- [Optimuslogic Systems India](https://computeexpresslink.org/member/optimuslogic-systems-india/)
- [PETAiO Inc](https://computeexpresslink.org/member/petaio-inc/)
- [PEZY Computing K.K.](https://computeexpresslink.org/member/pezy-computing-k-k/)
- [Phoenix Technologies Ltd.](https://computeexpresslink.org/member/phoenix-technologies-ltd/)
- [Phytium Technologies Co., Ltd.](https://computeexpresslink.org/member/phytium-technologies-co-ltd/)
- [Powerchip Semiconductor Manufacturing Corp (PSMC)](https://computeexpresslink.org/member/powerchip-semiconductor-manufacturing-corp-psmc/)
- [Preferred Networks, Inc.](https://computeexpresslink.org/member/preferred-networks-inc/)
- [Prodapt Technologies](https://computeexpresslink.org/member/prodapt-technologies/)
- [PRO DESIGN Electronic GmbH](https://computeexpresslink.org/member/pro-design-electronic-gmbh/)
- [Prodigy Technovations PVT LTD](https://computeexpresslink.org/member/prodigy-technovations-pvt-ltd/)
- [Quanta Computer Inc.](https://computeexpresslink.org/member/quanta-computer-inc/)
- [Rapid Silicon US Inc](https://computeexpresslink.org/member/rapid-silicon-us-inc/)
- [Gen X Computing](https://computeexpresslink.org/member/gen-x-computing/)
- [GateStor Data Systems Corporation](https://computeexpresslink.org/member/gatestor-data-systems-corporation/)
- [G2M Communications](https://computeexpresslink.org/member/g2m-communications/)
- [Fungible Inc.](https://computeexpresslink.org/member/fungible-inc/)
- [ForwardEdge ASIC, LLC](https://computeexpresslink.org/member/forwardedge-asic-llc/)
- [Flex Ltd.](https://computeexpresslink.org/member/flex-ltd/)
- [FLC Technology Group](https://computeexpresslink.org/member/flc-technology-group/)
- [Fine Point Technologies Inc](https://computeexpresslink.org/member/fine-point-technologies-inc/)
- [Fermionic Design Private Limited](https://computeexpresslink.org/member/fermionic-design-private-limited/)
- [Faraday Technology Corp.](https://computeexpresslink.org/member/faraday-technology-corp/)
- [ETRI](https://computeexpresslink.org/member/etri/)
- [eTopus Technology Inc](https://computeexpresslink.org/member/etopus-technology-inc/)
- [Elsys America](https://computeexpresslink.org/member/elsys-america/)
- [eInfochips Inc](https://computeexpresslink.org/member/einfochips-inc/)
- [Eideticom](https://computeexpresslink.org/member/eideticom/)
- [Echostreams Innovative Solutions LLC.](https://computeexpresslink.org/member/echostreams-innovative-solutions-llc/)
- [Durham University](https://computeexpresslink.org/member/durham-university/)
- [Drut Technologies Inc.](https://computeexpresslink.org/member/drut-technologies-inc/)
- [Dileep Neural Network](https://computeexpresslink.org/member/dileep-neural-network/)
- [DapuStor Corporation](https://computeexpresslink.org/member/dapustor-corporation/)
- [Cyan Semiconductor Co Ltd](https://computeexpresslink.org/member/cyan-semiconductor-co-ltd/)
- [Cornelis Networks, Inc.](https://computeexpresslink.org/member/cornelis-networks-inc/)
- [Clustered Systems](https://computeexpresslink.org/member/clustered-systems/)
- [Circuit Blvd., Inc.](https://computeexpresslink.org/member/circuit-blvd-inc/)
- [CIMware Pvt. Ltd](https://computeexpresslink.org/member/cimware-pvt-ltd/)
- [Chronos Tech](https://computeexpresslink.org/member/chronos-tech/)
- [Chelsio Comminications Inc.](https://computeexpresslink.org/member/chelsio-comminications-inc/)
- [Changxin Memory Technologies Inc](https://computeexpresslink.org/member/changxin-memory-technologies-inc/)
- [Centre for Development of Advanced Computing (CDAC)](https://computeexpresslink.org/member/centre-for-development-of-advanced-computing-cdac/)
- [Celestica](https://computeexpresslink.org/member/celestica/)
- [CAMEL](https://computeexpresslink.org/member/camel/)
- [California Memory Technologies IC. (Memtech)](https://computeexpresslink.org/member/california-memory-technologies-ic-memtech/)
- [Bloombase](https://computeexpresslink.org/member/bloombase/)
- [Bellwether Electronic Corp.](https://computeexpresslink.org/member/bellwether-electronic-corp/)
- [Beijing Uniexceeding Technology Co., Ltd.](https://computeexpresslink.org/member/beijing-uniexceeding-technology-co-ltd/)
- [Beijing Starblaze Technology Co. LTD.](https://computeexpresslink.org/member/beijing-starblaze-technology-co-ltd/)
- [Beijing Memblaze Technology Co., Ltd.](https://computeexpresslink.org/member/beijing-memblaze-technology-co-ltd/)
- [Beijing ESWIN Computing Technology Co., Ltd.](https://computeexpresslink.org/member/beijing-eswin-computing-technology-co-ltd/)
- [Ayar Labs](https://computeexpresslink.org/member/ayar-labs/)
- [ATP Electronics, Inc.​](https://computeexpresslink.org/member/atp-electronics-inc/)
- [ATG Consultants Inc.](https://computeexpresslink.org/member/atg-consultants-inc/)
- [ASUSTek Computer Inc.](https://computeexpresslink.org/member/asustek-computer-inc/)
- [ASRock Rack Inc.](https://computeexpresslink.org/member/asrock-rack-inc/)
- [Apacer Technology Inc.](https://computeexpresslink.org/member/apacer-technology-inc/)
- [Anritsu Corporation](https://computeexpresslink.org/member/anritsu-corporation/)
- [AMI US Holdings Inc.](https://computeexpresslink.org/member/ami-us-holdings-inc/)
- [AIC Inc.](https://computeexpresslink.org/member/aic-inc/)
- [Aeponyx Inc.](https://computeexpresslink.org/member/aeponyx-inc/)
- [ADTEC Corporation](https://computeexpresslink.org/member/adtec-corporation/)
- [Achronix Semiconductor Corporation](https://computeexpresslink.org/member/achronix-semiconductor-corporation/)
- [Accipiter Systems Inc](https://computeexpresslink.org/member/accipiter-systems-inc/)
- [Accelerated Tech, Inc](https://computeexpresslink.org/member/accelerated-tech-inc/)
- [6Harmonics Inc.](https://computeexpresslink.org/member/6harmonics-inc/)
- [Amphenol](https://computeexpresslink.org/member/amphenol/)
- [Ampere](https://computeexpresslink.org/member/ampere/)
- [Alpawave IP](https://computeexpresslink.org/member/alpawave-ip/)
- [Dell](https://computeexpresslink.org/member/dell/)
- [Cisco](https://computeexpresslink.org/member/cisco/)
- [AMD](https://computeexpresslink.org/member/amd/)
- [Alibaba](https://computeexpresslink.org/member/alibaba/)

## Press Room

- [Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs](https://computeexpresslink.org/news/synopsys-delivers-industrys-first-compute-express-link-cxl-ip-solution-for-breakthrough-performance-in-data-intensive-socs/)
- [Mobiveil Announces Availability of Compute Express Link (CXL) IP (COMPEX) for High-Performance Applications](https://computeexpresslink.org/news/mobiveil-announces-availability-of-compute-express-link-cxl-ip-compex-for-high-performance-applications/)
- [Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs](https://computeexpresslink.org/news/synopsys-designware-cxl-ip-supports-amba-cxs-protocol-targeting-high-performance-computing-socs/)
- [SiPearl Joins the CXL® Consortium Behind Compute Express Link®, the Breakthrough CPU-to-Device Interconnect](https://computeexpresslink.org/news/sipearl-joins-the-cxl-consortium-behind-compute-express-link-the-breakthrough-cpu-to-device-interconnect/)
- [Microchip Extends Leadership in Data Center Connectivity with Industry’s Lowest Latency PCI Express 5.0 and CXL 2.0 Retimers](https://computeexpresslink.org/news/microchip-extends-leadership-in-data-center-connectivity-with-industrys-lowest-latency-pci-express-5-0-and-cxl-2-0-retimers/)
- [Synopsys Announces Industry's First CXL 2.0 VIP Solution for Breakthrough SoC Performance](https://computeexpresslink.org/news/synopsys-announces-industrys-first-cxl-2-0-vip-solution-for-breakthrough-soc-performance/)
- [Astera Labs Expands Focus to Deliver Purpose-Built Solutions That Address Connectivity Bottlenecks Throughout the Data Center](https://computeexpresslink.org/news/astera-labs-expands-focus-to-deliver-purpose-built-solutions-that-address-connectivity-bottlenecks-throughout-the-data-center/)
- [Avery Design Debuts CXL® 2.0 System-level VIP Simulation Solution](https://computeexpresslink.org/news/avery-design-debuts-cxl-2-0-system-level-vip-simulation-solution/)
- [Samsung Unveils Industry-First Memory Module Incorporating New CXL Interconnect Standard](https://computeexpresslink.org/news/samsung-unveils-industry-first-memory-module-incorporating-new-cxl-interconnect-standard/)
- [Tear Down These Walls: How CXL Could Reinvent the Data Center](https://computeexpresslink.org/news/tear-down-these-walls-how-cxl-could-reinvent-the-data-center/)
- [CXL Signals A New Era Of Data Center Architecture](https://computeexpresslink.org/news/cxl-signals-a-new-era-of-data-center-architecture/)
- [How CXL is Changing the Data Center](https://computeexpresslink.org/news/how-cxl-is-changing-the-data-center/)
- [Securing Server Systems And Data At The Hardware Level](https://computeexpresslink.org/news/securing-server-systems-and-data-at-the-hardware-level/)
- [CXL Product Pipeline Gets Flowing](https://computeexpresslink.org/news/cxl-product-pipeline-gets-flowing/)
- [Intel Hot Interconnects 2021 CXL Keynote Coverage](https://computeexpresslink.org/news/intel-hot-interconnects-2021-cxl-keynote-coverage/)
- [The CXL Roadmap Opens Up the Memory Hierarchy](https://computeexpresslink.org/news/the-cxl-roadmap-opens-up-the-memory-hierarchy/)
- [CXL Ushers in a New Era of Data-Center Architecture](https://computeexpresslink.org/news/cxl-ushers-in-a-new-era-of-data-center-architecture/)
- [CXL and the Tiered-Memory Future of Servers](https://computeexpresslink.org/news/cxl-and-the-tiered-memory-future-of-servers/)
- [Heterogeneous Computing Is About Optimizing Resources](https://computeexpresslink.org/news/heterogeneous-computing-is-about-optimizing-resources/)
- [Elastics.cloud Announces Strategic Investment by SK hynix](https://computeexpresslink.org/news/elastics-cloud-announces-strategic-investment-by-sk-hynix/)
- [Tanzanite Silicon Solutions Demonstrates Industry’s First CXL Based Memory Expansion and Memory Pooling Products, Ushering in the Era of Next Generation Composable Data Centers](https://computeexpresslink.org/news/tanzanite-silicon-solutions-demonstrates-industrys-first-cxl-based-memory-expansion-and-memory-pooling-products-ushering-in-the-era-of-next-generation-composable-data-centers/)
- [Astera Labs Unlocks Next-Gen Cloud Connectivity with Aries PCIe® 5.0 and CXL® 2.0 Smart Retimers Production Release](https://computeexpresslink.org/news/astera-labs-unlocks-next-gen-cloud-connectivity-with-aries-pcie-5-0-and-cxl-2-0-smart-retimers-production-release/)
- [Elastics.cloud, Inc. Announces an Additional $17M of Funding to Accelerate Global Growth and Product Development​](https://computeexpresslink.org/news/elastics-cloud-inc-announces-an-additional-17m-of-funding-to-accelerate-global-growth-and-product-development/)
- [Montage Technology Delivers the World’s First CXL® Memory eXpander Controller​](https://computeexpresslink.org/news/montage-technology-delivers-the-worlds-first-cxl-memory-expander-controller/)
- [MemVerge Hosts Full-Day Forum, "CXL: Getting Ready for Takeoff," at the Flash Memory Summit​](https://computeexpresslink.org/news/memverge-hosts-full-day-forum-cxl-getting-ready-for-takeoff-at-the-flash-memory-summit/)
- [Microchip Introduces New CXL® Smart Memory Controllers for Data Center Computing Enabling Modern CPUs to Optimize Application Workloads​](https://computeexpresslink.org/news/microchip-introduces-new-cxl-smart-memory-controllers-for-data-center-computing-enabling-modern-cpus-to-optimize-application-workloads/)
- [Astera Labs Enters Pre-Production Phase of Leo Memory Connectivity Platform for CXL-Attached Memory Expansion and Pooling](https://computeexpresslink.org/news/astera-labs-enters-pre-production-phase-of-leo-memory-connectivity-platform-for-cxl-attached-memory-expansion-and-pooling/)
- [Astera Labs Introduces Industry’s First CXL® 2.0 Memory Accelerator SoC Platform](https://computeexpresslink.org/news/astera-labs-introduces-industrys-first-cxl-2-0-memory-accelerator-soc-platform/)
- [Elastics.cloud Adds Key Leadership Talent to Their Team](https://computeexpresslink.org/news/elastics-cloud-adds-key-leadership-talent-to-their-team/)
- [Astera Labs Launches Cloud-Scale Interop Lab to Enable Seamless Deployment of CXL Solutions at Scale](https://computeexpresslink.org/news/astera-labs-launches-cloud-scale-interop-lab-to-enable-seamless-deployment-of-cxl-solutions-at-scale/)
- [Enabling New Server Architectures With the CXL Interconnect](https://computeexpresslink.org/news/enabling-new-server-architectures-with-the-cxl-interconnect-2/)
- [Astera Labs First to Break Through the Memory Wall with Industry’s Highest Performance CXL Memory Controllers](https://computeexpresslink.org/news/astera-labs-first-to-break-through-the-memory-wall-with-industrys-highest-performance-cxl-memory-controllers/)
- [Micron Launches Memory Expansion Module Portfolio to Accelerate CXL 2.0 Adoption](https://computeexpresslink.org/news/micron-launches-memory-expansion-module-portfolio-to-accelerate-cxl-2-0-adoption/)
- [Industry Heavyweights Get Behind Data Centre Optimisation Effort For Artificial Intelligence – Data Economy](https://computeexpresslink.org/news/industry-heavyweights-get-behind-data-centre-optimisation-effort-for-artificial-intelligence-data-economy/)
- [CXL Consortium Launches CPU-to-Anything High Speed Interconnect Protocol – HPCWire](https://computeexpresslink.org/news/cxl-consortium-launches-cpu-to-anything-high-speed-interconnect-protocol-hpcwire/)
- [Tech Giants To Team Up For Boosting CXL Consortium Data Centre Performance – Analytics Insight](https://computeexpresslink.org/news/tech-giants-to-team-up-for-boosting-cxl-consortium-data-centre-performance-analytics-insight/)
- [How are faster networks advancing the next generation of data centres? – Cloud Computing](https://computeexpresslink.org/news/how-are-faster-networks-advancing-the-next-generation-of-data-centres-cloud-computing/)
- [Compute Express Link (CXL): From Nine Members to Thirty Three – AnandTech](https://computeexpresslink.org/news/compute-express-link-cxl-from-nine-members-to-thirty-three-anandtech/)
- [AMD Joins CXL Consortium: Playing in All The Interconnects – AnandTech](https://computeexpresslink.org/news/amd-joins-cxl-consortium-playing-in-all-the-interconnects-anandtech/)
- [ARM Joins CXL Consortium – HPCWire](https://computeexpresslink.org/news/arm-joins-cxl-consortium-hpcwire/)
- [CXL Consortium Formally Incorporated, Gets New Board Members & CXL 1.1 Specification – AnandTech](https://computeexpresslink.org/news/cxl-consortium-formally-incorporated-gets-new-board-members-cxl-1-1-specification-anandtech/)
- [CXL Enables Heterogenous Computing – Forbes](https://computeexpresslink.org/news/cxl-enables-heterogenous-computing-forbes/)
- [CXL and Gen-Z Iron Out A Coherent Interconnect Strategy – The Next Platform](https://computeexpresslink.org/news/cxl-and-gen-z-iron-out-a-coherent-interconnect-strategy-the-next-platform/)
- [Memory-Centric Architectures With Gen-Z And CXL Alliance – Forbes](https://computeexpresslink.org/news/memory-centric-architectures-with-gen-z-and-cxl-alliance-forbes/)
- [CXL and Gen-Z Lay Borders with a Formal MOU We Talk Impact – ServeTheHome](https://computeexpresslink.org/news/cxl-and-gen-z-lay-borders-with-a-formal-mou-we-talk-impact-servethehome/)
- [CXL Protocol Adds Capabilities over PCIe – EETimes](https://computeexpresslink.org/news/cxl-protocol-adds-capabilities-over-pcie-eetimes/)
- [Compute Express Link CXL 2.0 Specification Released the Big One – ServeTheHome](https://computeexpresslink.org/news/compute-express-link-cxl-2-0-specification-released-the-big-one-servethehome/)
- [Compute eXpress Link 2.0 (CXL 2.0) Finalized: Switching, PMEM, Security – AnandTech](https://computeexpresslink.org/news/compute-express-link-2-0-cxl-2-0-finalized-switching-pmem-security-anandtech/)
- [CXL gathers speed with 2.0 spec – EE Times](https://computeexpresslink.org/news/cxl-gathers-speed-with-2-0-spec-ee-times/)
- [Domain-Specific Memory – Semiconductor Engineering](https://computeexpresslink.org/news/domain-specific-memory-semiconductor-engineering/)
- [CXL: Coherency, Memory, and I/O Semantics on PCIe Infrastructure – Electronic Design](https://computeexpresslink.org/news/cxl-coherency-memory-and-i-o-semantics-on-pcie-infrastructure-electronic-design/)
- [Compute Express Link or CXL What it is and Examples – Serve the Home](https://computeexpresslink.org/news/compute-express-link-or-cxl-what-it-is-and-examples-serve-the-home/)
- [Planning for Servers in 2022 and Beyond Series – Serve the Home](https://computeexpresslink.org/news/planning-for-servers-in-2022-and-beyond-series-serve-the-home/)
- [And so it comes to pass: Gen-Z will be folded into CXL – Blocks & Files](https://computeexpresslink.org/news/and-so-it-comes-to-pass-gen-z-will-be-folded-into-cxl-blocks-files/)
- [Big Memory Needs Software-defined Memory – DCIG](https://computeexpresslink.org/news/big-memory-needs-software-defined-memory-dcig/)
- [CXL Consortium Showcases First Public Demonstrations of Compute Express Link Technology at SC21 – HPCwire](https://computeexpresslink.org/news/cxl-consortium-showcases-first-public-demonstrations-of-compute-express-link-technology-at-sc21-hpcwire/)
- [CXL Consortium at SC21: 1st Public Demo of Compute Express Link – insideHPC](https://computeexpresslink.org/news/cxl-consortium-at-sc21-1st-public-demo-of-compute-express-link-insidehpc/)
- [Finally, A Coherent Interconnect Strategy: CXL Absorbs Gen-Z – The Next Platform](https://computeexpresslink.org/news/finally-a-coherent-interconnect-strategy-cxl-absorbs-gen-z-the-next-platform/)
- [Top 10 Showcases at Supercomputing 2021 – Serve the Home](https://computeexpresslink.org/news/top-10-showcases-at-supercomputing-2021-serve-the-home/)
- [Intel Sapphire Rapids CXL with Emmitsburg PCH Shown at SC21 – Serve the Home](https://computeexpresslink.org/news/intel-sapphire-rapids-cxl-with-emmitsburg-pch-shown-at-sc21-serve-the-home/)
- [CXL Will Absorb Gen-Z - EE Times](https://computeexpresslink.org/news/cxl-will-absorb-gen-z-ee-times/)
- [CXL Put Through Its Paces - EE Times](https://computeexpresslink.org/news/cxl-put-through-its-paces-ee-times/)
- [Data centre disaggregation with Gen-Z and CXL - Gazettabyte](https://computeexpresslink.org/news/data-centre-disaggregation-with-gen-z-and-cxl-gazettabyte/)
- [Virtual Roundtable On Storage And Memory - Forbes](https://computeexpresslink.org/news/virtual-roundtable-on-storage-and-memory-forbes/)
- [Choosing The Right Server Interface Architectures For High Performance Computing - Semiconductor Engineering](https://computeexpresslink.org/news/choosing-the-right-server-interface-architectures-for-high-performance-computing-semiconductor-engineering/)
- [One Memory to Rule Them All: The Rise of CXL - Embedded Computing Design](https://computeexpresslink.org/news/one-memory-to-rule-them-all-the-rise-of-cxl-embedded-computing-design/)
- [How CXL may change the datacenter as we know it - The Register](https://computeexpresslink.org/news/how-cxl-may-change-the-datacenter-as-we-know-it-the-register/)
- [Four key need-to-knows about CXL - ComputerWeekly](https://computeexpresslink.org/news/four-key-need-to-knows-about-cxl-computerweekly/)
- [OpenCAPI to Be Folded into CXL – HPCwire](https://computeexpresslink.org/news/opencapi-to-be-folded-into-cxl-hpcwire/)
- [Compute Express Link (CXL) 3.0 Announced: Doubled Speeds and Flexible Fabrics – Anandtech](https://computeexpresslink.org/news/compute-express-link-cxl-3-0-announced-doubled-speeds-and-flexible-fabrics-anandtech/)
- [CXL Brings Datacenter-sized Computing with 3.0 Standard, Thinks Ahead to 4.0 – HPCwire](https://computeexpresslink.org/news/cxl-brings-datacenter-sized-computing-with-3-0-standard-thinks-ahead-to-4-0-hpcwire/)
- [Why you should start paying attention to CXL now – The Register](https://computeexpresslink.org/news/why-you-should-start-paying-attention-to-cxl-now-the-register/)
- [Compute Express Link CXL 3.0 is the Exciting Building Block for Disaggregation – ServeTheHome](https://computeexpresslink.org/news/compute-express-link-cxl-3-0-is-the-exciting-building-block-for-disaggregation-servethehome/)
- [Flash memory vendors unveil PCIe 5.0 SSDs, latest spec for CXL interconnect tech – The Register](https://computeexpresslink.org/news/flash-memory-vendors-unveil-pcie-5-0-ssds-latest-spec-for-cxl-interconnect-tech-the-register/)
- [CXL Ecosystem Enabling Memory Fabrics – Forbes](https://computeexpresslink.org/news/cxl-ecosystem-enabling-memory-fabrics-forbes/)
- [CXL Spec Grows, Absorbs Others to Collate Ecosystem – EE Times](https://computeexpresslink.org/news/cxl-spec-grows-absorbs-others-to-collate-ecosystem-ee-times/)
- [A primer on CXL technology uses – SearchStorage](https://computeexpresslink.org/news/a-primer-on-cxl-technology-uses-searchstorage/)
- [SNIA Spec Gets Data Moving in CXL Environment - EE Times](https://computeexpresslink.org/news/snia-spec-gets-data-moving-in-cxl-environment-ee-times/)
- [How the CXL Consortium is Driving Adoption with Siamak Tavallaei | Utilizing Tech 4×14](https://computeexpresslink.org/news/how-the-cxl-consortium-is-driving-adoption-with-siamak-tavallaei-utilizing-tech-4x14/)
- [Memory At The 2023 Designcon](https://computeexpresslink.org/news/memory-at-the-2023-designcon/)
- [DesignCon 2023 A Hotbed for Technology Discussion](https://computeexpresslink.org/news/designcon-2023-a-hotbed-for-technology-discussion/)
- [The History and Future of CXL with Jim Pappas | Utilizing Tech 4×20](https://computeexpresslink.org/news/the-history-and-future-of-cxl-with-jim-pappas-utilizing-tech-4x20/)
- [A Game-Changing Approach, New Mergers and a Disruptive Technology with Siamak Tavallaei from the CXL Consortium](https://computeexpresslink.org/news/a-game-changing-approach-new-mergers-and-a-disruptive-technology-with-siamak-tavallaei-from-the-cxl-consortium/)
- [How DPUs, IPUs, and CXL Can Improve Data Center Power Efficiency](https://computeexpresslink.org/news/how-dpus-ipus-and-cxl-can-improve-data-center-power-efficiency/)
- [How CXL 3.0 technology will affect enterprise storage](https://computeexpresslink.org/news/how-cxl-3-0-technology-will-affect-enterprise-storage/)
- [Unveiling the Future of Memory and Storage: Insights FMS2023](https://computeexpresslink.org/news/unveiling-the-future-of-memory-and-storage-insights-fms2023/)
- [Realizing the Potential of CXL with Jim Pappas and Kurtis Bowman](https://computeexpresslink.org/news/realizing-the-potential-of-cxl-with-jim-pappas-and-kurtis-bowman/)
- [CXL in the datacentre: Boosting memory for hungry workloads](https://computeexpresslink.org/news/cxl-in-the-datacentre-boosting-memory-for-hungry-workloads/)
- [CXL Consortium Set to Present and Showcase Technology Demonstrations at SC’22 in Dallas, TX – HPCwire](https://computeexpresslink.org/news/cxl-consortium-set-to-present-and-showcase-technology-demonstrations-at-sc22-in-dallas-tx-hpcwire/)
- [Latest CXL Spec Lined up to Support DDR6](https://computeexpresslink.org/news/latest-cxl-spec-lined-up-to-support-ddr6/)
- [HPCwire Reveals Winners of the 2022 Readers’ and Editors’ Choice Awards During SC22 – HPCwire](https://computeexpresslink.org/news/hpcwire-reveals-winners-of-the-2022-readers-and-editors-choice-awards-during-sc22-hpcwire/)
- [SC23: TOP500 Trends, the AI-HPC Crossover, Chiplet Standardization, the Emergence of UCIe and CXL Advancements](https://computeexpresslink.org/news/sc23-top500-trends-the-ai-hpc-crossover-chiplet-standardization-the-emergence-of-ucie-and-cxl-advancements/)
- [CXL 3.1 Specification Aims for Big Topologies](https://computeexpresslink.org/news/cxl-3-1-specification-aims-for-big-topologies/)
- [Key Industry Player Converge to Advance CXL®, a New High-Speed  CPU Interconnect for Breakthrough Data Center Performance](https://computeexpresslink.org/news/key-industry-player-converge-to-advance-cxl-a-new-high-speed-cpu-interconnect-for-breakthrough-data-center-performance/)
- [CXL® Promoter Statements of Support](https://computeexpresslink.org/news/cxl-promoter-statements-of-support/)
- [Compute Express Link® Consortium (CXL®) Officially Incorporates; Announces Expanded Board of Directors](https://computeexpresslink.org/news/compute-express-link-consortium-cxl-officially-incorporates-announces-expanded-board-of-directors/)
- [CXL® Consortium and Gen-Z Consortium Announce MOU Agreement](https://computeexpresslink.org/news/cxl-consortium-and-gen-z-consortium-announce-mou-agreement/)
- [CXL® Consortium Releases Compute Express Link® 2.0 Specification](https://computeexpresslink.org/news/cxl-consortium-releases-compute-express-link-2-0-specification/)
- [CXL® Consortium Members Statements of Support for CXL 2.0](https://computeexpresslink.org/news/cxl-consortium-members-statements-of-support-for-cxl-2-0/)
- [CXL Consortium Showcases First Public Demonstrations of Compute Express Link Technology at Supercomputing 2021](https://computeexpresslink.org/news/cxl-consortium-showcases-first-public-demonstrations-of-compute-express-link-technology-at-supercomputing-2021/)
- [CXL Consortium Signs Agreement with Gen-Z Consortium to Accept Transfer of Gen-Z Specifications and Assets](https://computeexpresslink.org/news/cxl-consortium-signs-agreement-with-gen-z-consortium-to-accept-transfer-of-gen-z-specifications-and-assets/)
- [CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL](https://computeexpresslink.org/news/cxl-consortium-and-opencapi-consortium-sign-letter-of-intent-to-transfer-opencapi-specifications-to-cxl/)
- [CXL® Consortium Members – Statements of Support for CXL 3.0 Specification](https://computeexpresslink.org/news/cxl-consortium-members-statements-of-support-for-cxl-3-0-specification/)
- [CXL Consortium releases Compute Express Link 3.0 specification to expand fabric capabilities and management](https://computeexpresslink.org/news/cxl-consortium-releases-compute-express-link-3-0-specification-to-expand-fabric-capabilities-and-management/)
- [CXL Consortium and JEDEC Sign MOU Agreement to Advance DRAM and Persistent Memory Technology](https://computeexpresslink.org/news/cxl-consortium-and-jedec-sign-mou-agreement-to-advance-dram-and-persistent-memory-technology/)
- [CXL Consortium announces Compute Express Link 3.1 specification release](https://computeexpresslink.org/news/cxl-consortium-announces-compute-express-link-3-1-specification-release/)
- [CXL® Consortium Members – Statements of Support for CXL 3.1 Specification](https://computeexpresslink.org/news/cxl-consortium-members-statements-of-support-for-cxl-3-1-specification/)
- [MWC 2026: SK Telecom and Panmnesia Sign Partnership to Innovate AI Data Center Architecture, Enhancing Cost Efficiency and Performance](https://computeexpresslink.org/news/mwc-2026-sk-telecom-and-panmnesia-sign-partnership-to-innovate-ai-data-center-architecture-enhancing-cost-efficiency-and-performance/)
- [Compute Express Link Consortium debuts 4.0 spec to push past bandwidth bottlenecks](https://computeexpresslink.org/news/compute-express-link-consortium-debuts-4-0-spec-to-push-past-bandwidth-bottlenecks/)
- [CXL Supports Higher Performance And DDN Enables Sovereign AI At SC25](https://computeexpresslink.org/news/cxl-supports-higher-performance-and-ddn-enables-sovereign-ai-at-sc25/)
- [CXL Adds Port Bundling to Quench AI Thirst](https://computeexpresslink.org/news/cxl-adds-port-bundling-to-quench-ai-thirst/)
- [CXL Consortium Members – Statements of Support for CXL 4.0 Specification](https://computeexpresslink.org/news/cxl-consortium-members-statements-of-support-for-cxl-4-0-specification/)
- [CXL Consortium Releases the Compute Express Link 4.0 Specification Increasing Speed and Bandwidth](https://computeexpresslink.org/news/cxl-consortium-releases-the-compute-express-link-4-0-specification-increasing-speed-and-bandwidth/)
- [Compute Can't Handle the Truth: Why Communication Tax Prioritizes Memory and Interconnects in Modern AI Infrastructure](https://computeexpresslink.org/news/compute-cant-handle-the-truth-why-communication-tax-prioritizes-memory-and-interconnects-in-modern-ai-infrastructure/)
- [Panmnesia Introduces Today’s and Tomorrow’s AI Infrastructure, Including a Supercluster Architecture That Integrates NVLink, UALink, and HBM via CXL](https://computeexpresslink.org/news/panmnesia-introduces-todays-and-tomorrows-ai-infrastructure-including-a-supercluster-architecture-that-integrates-nvlink-ualink-and-hbm-via-cxl/)
- [Optimizing Data Center TCO With CXL And Compression](https://computeexpresslink.org/news/optimizing-data-center-tco-with-cxl-and-compression/)
- [Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel® Xeon® 6 Processors](https://computeexpresslink.org/news/optimizing-system-memory-bandwidth-with-micron-cxl-memory-expansion-modules-on-intel-xeon-6-processors/)
- [CXL Update Emphasizes Security](https://computeexpresslink.org/news/cxl-update-emphasizes-security/)
- [CXL is Finally Coming in 2025](https://computeexpresslink.org/news/cxl-is-finally-coming-in-2025/)
- [CXL gains Big Mo as memory chokes on AI workloads](https://computeexpresslink.org/news/cxl-gains-big-mo-as-memory-chokes-on-ai-workloads/)
- [CXL memory: The key to unlocking high-performance computing in modern data centers](https://computeexpresslink.org/news/cxl-memory-the-key-to-unlocking-high-performance-computing-in-modern-data-centers/)
- [CXL for Memory and More](https://computeexpresslink.org/news/cxl-for-memory-and-more/)
- [Crucial tech that's pivotal for AI in hyperscalers gets major update to improve performance, enhance functionality and extend security](https://computeexpresslink.org/news/crucial-tech-thats-pivotal-for-ai-in-hyperscalers-gets-major-update-to-improve-performance-enhance-functionality-and-extend-security/)
- [CXL Consortium Announces Compute Express Link 3.2 Specification Release](https://computeexpresslink.org/news/cxl-consortium-announces-compute-express-link-3-2-specification-release/)
- [Teledyne LeCroy Unveils Next-Generation CXL™ 2.0 Device Validation Solution](https://computeexpresslink.org/news/teledyne-lecroy-unveils-next-generation-cxl-2-0-device-validation-solution/)
- [CXL Thriving As Memory Link](https://computeexpresslink.org/news/cxl-thriving-as-memory-link/)
- [CXL moves forward as memory technology for AI](https://computeexpresslink.org/news/cxl-moves-forward-as-memory-technology-for-ai/)
- [CXL Gathers Momentum at FMS 2024](https://computeexpresslink.org/news/cxl-gathers-momentum-at-fms-2024/)
- [What is “Stranded Memory?”](https://computeexpresslink.org/news/what-is-stranded-memory/)
- [CXL Brings Even More Memory to the Cloud](https://computeexpresslink.org/news/cxl-brings-even-more-memory-to-the-cloud/)
- [Teledyne LeCroy Announces Industry-First Compute Express Link™ (CXL) Device Validation Solution](https://computeexpresslink.org/news/teledyne-lecroy-announces-industry-first-compute-express-link-cxl-device-validation-solution/)
- [Composable Memory within CXL 2.0 Protocol Shown by Liqid, Samsung, Tanzanite](https://computeexpresslink.org/news/composable-memory-within-cxl-2-0-protocol-shown-by-liqid-samsung-tanzanite-2/)
- [Enabling New Server Architectures With the CXL Interconnect](https://computeexpresslink.org/news/enabling-new-server-architectures-with-the-cxl-interconnect/)
- [Composable Memory within CXL 2.0 Protocol Shown by Liqid, Samsung, Tanzanite](https://computeexpresslink.org/news/composable-memory-within-cxl-2-0-protocol-shown-by-liqid-samsung-tanzanite/)
- [Intel, Google and others join forces for CXL interconnect – Data Center Dynamics](https://computeexpresslink.org/news/intel-google-and-others-join-forces-for-cxl-interconnect-data-center-dynamics/)
- [New CXL interconnect promises to move data faster, more efficiently at 32 GT/s – VentureBeat](https://computeexpresslink.org/news/new-cxl-interconnect-promises-to-move-data-faster-more-efficiently-at-32-gt-s-venturebeat/)
- [Safeguarding Data Over PCIe & CXL in Data Centers – Semiconductor Engineering](https://computeexpresslink.org/news/safeguarding-data-over-pcie-cxl-in-data-centers-semiconductor-engineering/)
- [How the CXL interconnect will affect enterprise storage – Tech Target](https://computeexpresslink.org/news/how-the-cxl-interconnect-will-affect-enterprise-storage-tech-target/)
- [Top 5 Data Center Tech to Watch in 2022 - SDxCentral](https://computeexpresslink.org/news/top-5-data-center-tech-to-watch-in-2022-sdxcentral/)
- [What’s the Difference Between CXL 1.1 and CXL 2.0? – ElectronicDesign](https://computeexpresslink.org/news/whats-the-difference-between-cxl-1-1-and-cxl-2-0-electronicdesign/)
- [MEMCON 2024: Insights into CXL, HBM, GenAI, and More](https://computeexpresslink.org/news/memcon-2024-insights-into-cxl-hbm-genai-and-more/)
- [CXL Gets Off the Drawing Board](https://computeexpresslink.org/news/cxl-gets-off-the-drawing-board/)
- [CXL: The Future Of Memory Interconnect?](https://computeexpresslink.org/news/cxl-the-future-of-memory-interconnect/)

## Resources

- [CXL 1.1 Technical Training](https://computeexpresslink.org/resource/cxl-1-1-technical-training/) - © 2022 Compute Express Link Consortium, Inc. RIGHTS RESERVED. By continuing to view or use this video (“Video”), and/or by agreeing to this notice, you (“you”) hereby agree to the following terms and conditions: (i) This Video, and all copyrights and other intellectual property rights in and to this Video, are solely owned by Compute
- [CXL 2.0 Technical Training](https://computeexpresslink.org/resource/cxl-2-0-technical-training/) - © 2022 Compute Express Link Consortium, Inc. RIGHTS RESERVED. By continuing to view or use this video (“Video”), and/or by agreeing to this notice, you (“you”) hereby agree to the following terms and conditions: (i) This Video, and all copyrights and other intellectual property rights in and to this Video, are solely owned by Compute
- [XConn's CXL 2.0 Switch: Memory Pooling and Memory Sharing](https://computeexpresslink.org/resource/xconns-cxl-2-0-switch-memory-pooling-and-memory-sharing/) - Learn more by visiting www.xconn-tech.com.
- [Synopsys and Teledyne LeCroy Perform First CXL 2.0 IP Interop Demo with Compliance Tests](https://computeexpresslink.org/resource/synopsys-and-teledyne-lecroy-perform-first-cxl-2-0-ip-interop-demo-with-compliance-tests/) - Synopsys' CXL 2.0 IP compliance tests and interoperability using Teledyne LeCroy Summit T54 analyzer and Summit Z516 Exerciser to showcase performance and operation. Summit T54 Analyzer - The Summit T54 Protocol Analyzer captures, decodes and displays PCIe 5.0 protocol traffic data rates for x1, x2, x4 lane widths. Summit Z516 Exerciser - The Summit Z516 is a
- [Experience Reality, Not Blueprints: Panmnesia’s Real-World, Multi-Terabyte CXL Memory Disaggregation Showcase at Flash Memory Summit 2023 (FMS 23)](https://computeexpresslink.org/resource/experience-reality-not-blueprints-panmnesias-real-world-multi-terabyte-cxl-memory-disaggregation-showcase-at-flash-memory-summit-2023-fms-23/) - The video offers a comprehensive look at Panmnesia's unique CXL system, which includes custom-designed CXL CPUs, switches, and DIMM pools. This singular structure allows multi-terabyte capacity by consolidating numerous memory devices via layered CXL switches. Notably, our innovative DIMM pooling technology translates into substantial cost reductions. Moreover, the demonstration underscores the tangible advantages of genuine
- [Micron CZ120 memory expansion module for Data Intensive Workloads](https://computeexpresslink.org/resource/micron-cz120-memory-expansion-module-for-data-intensive-workloads/) - Demo will showcase Micron’s upcoming E3.S CXL 2.0 based memory expansion module. It will demonstrate performance enhancement of industry standard TPC-H, Machine Learning and HPC workloads using Micron’s CZ120 memory expansion product on fully populated AMD’s start of the art EPYC processors-based platforms with 12 DIMM channels, 128 cores and 8 SSDs. For more information
- [Liqid Composable CXL memory technology preview video](https://computeexpresslink.org/resource/liqid-composable-cxl-memory-technology-preview-video/) - With production Liqid composable software as the CXL fabric manager, Matrix demonstrates the real-time adding and removing of server memory from remote CXL memory pools, and migration between servers. Learn more by visiting https://www.liqid.com/ and https://www.youtube.com/@Liqid.
- [Elastics.cloud Rack-Scale Memory Pooling with CXL over Ethernet](https://computeexpresslink.org/resource/elastics-cloud-rack-scale-memory-pooling-with-cxl-over-ethernet/) - In this video, Elastics.cloud showcases its patent-pending CXL over Ethernet (COE) technology, demonstrating memory pooling at rack-scale. COE is a revolutionary approach to scaling existing server fabrics, bringing CXL connectivity into legacy datacenter frameworks, presenting significant system-level performance improvements while minimizing operational cost. ​ Learn more by visiting www.elastics.cloud and https://www.linkedin.com/company/elastics-cloud-inc/.
- [Industry’s First CXL 2.0 RAS Capabilities Demo with Leo Memory Connectivity Platform](https://computeexpresslink.org/resource/industrys-first-cxl-2-0-ras-capabilities-demo-with-leo-memory-connectivity-platform/) - With production In this video demo, Astera Labs shows how its Leo Memory Connectivity Platform supports cloud-scale fleet management with platform health monitoring, memory error detection & reporting capabilities. In addition, we showcase the first CXL memory controller to support DDR5 memory modules at 5600MT/s speed. Learn more at www.asteralabs.com/leo.
- [ZeroPoint Technologies: Hardware Accelerated CXL Memory Compression](https://computeexpresslink.org/resource/zeropoint-technologies-hardware-accelerated-cxl-memory-compression/) - ZeroPoint Technologies will demonstrate an integrated, Hardware Accelerated Compression Engine, seamlessly adding a new Compressed CXL Memory tier to the system Memory Hierarchy.Background: Hyperscaler end customers like Meta and Google employ software data compression today in production to tier memory into 3 level hierarchy: DRAM, software Compressed DRAM and SSD. They spend up to 5%
- [Xconn Technologies: CXL 2.0 Memory Pooling (Sharing) Using Xconn Switch](https://computeexpresslink.org/resource/xconn-technologies-cxl-2-0-memory-pooling-sharing-using-xconn-switch/) - XConn Technologies demos a composable memory system (CMS) through using XConn's CXL 2.0 switch and a number of CXL memory expander devices such as devices from Samsung, Micron and SmartModular. With the software from partner companies, XConn demoed a working prototype of memory pooling, and even further memory sharing through software support.
- [Viavi: CXL 2.0 Exerciser and Analyzer System](https://computeexpresslink.org/resource/viavi-cxl-2-0-exerciser-and-analyzer-system/) - VIAVI CXL protocol test solutions provide tools necessary to debug, analyze and perform validation of CXL links on an integrated exerciser and analyzer platform. To learn more visit: VIAVI CXL test solutions.
- [UniFabrix: MAXimize HPC and AI Speed with: MAX® memory and Storage Machine](https://computeexpresslink.org/resource/unifabrix-maximize-hpc-and-ai-speed-with-max-memory-and-storage-machine/) - Watch the UnifabriX MAX live demo! On-demand, workload-aware, high-performance provisioning of memory capacity and bandwidth! Welcome to the era of memory acceleration… Turbocharge your AI with UnifabriX MAX! Come see performance gain for industry-standard benchmarks.
- [Synopsys / Teledyne LeCroy: CXL 2.0 Interop and Compliance Testing with Teledyne LeCroy Summit Z516 Protocol Exerciser](https://computeexpresslink.org/resource/synopsys-teledyne-lecroy-cxl-2-0-interop-and-compliance-testing-with-teledyne-lecroy-summit-z516-protocol-exerciser/) - Teledyne LeCroy and Synopsys are showcasing at SC’23 protocol analysis and compliance testing of CXL based devices through a demo interop using Synopsys CXL 2.0 complete solution and the Teledyne LeCroy Summit Z516 Protocol Exerciser. Learn more about the Teledyne LeCroy CXL Protocol Analyzers and Exercisers here. Learn more about Synopsys CXL IP complete solution with controller,
- [Siemens EDA: CXL Performance Optimization & Validation SW Development Kit](https://computeexpresslink.org/resource/siemens-eda-cxl-performance-optimization-validation-sw-development-kit/) - Demonstrate targeted CXL Performance and Validation Suite under CPDK (CXL Performance Development Kit) running under Linux on a CXL 2.0/3.0 system. Demonstration targets include both pre-silicon QEMU/KVM/Co-Sim virtual environment and post-silicon Sapphire Rapids server with industry leading CXL memory expansion platforms.CPDK (CXL Performance Development Kit) supports performance benchmarking and validation framework for fine-grained verification and
- [Samsung: Graph DB Application on CXL Memory Enabled System](https://computeexpresslink.org/resource/samsung-graph-db-application-on-cxl-memory-enabled-system/) - By sharing the Nebula DB bench performance measurement using CXL Memory Expander (CMM-D), Samsung shows the potential benefits in various applications (in memory databases, AI training, etc.) of CMM-D. Due to an increase in data explosion & I/O traffic, a new protocol for CPU-accelerator and high capacity & bandwidth memory is needed. Samsung has been
- [Rambus: CXL Tiered Memory Platform Development Kit for Performant Memory Scaling](https://computeexpresslink.org/resource/rambus-cxl-tiered-memory-platform-development-kit-for-performant-memory-scaling/) - This demonstration will preview the high degree of flexibility and configurability offered by the Rambus CXL platform development kit (PDK). Benchmarking software will be running in a production server demonstrating the effective use of memory tiering through the Rambus CXL PDK. Audience members will be encouraged to customize and update the PDK’s behavior using in-box
- [Micron: Micron CZ120 Memory Capacity Expansion for AI & HPC Workloads Using CXL](https://computeexpresslink.org/resource/micron-micron-cz120-memory-capacity-expansion-for-ai-hpc-workloads-using-cxl/) - Our Live Demo shows with CXL not only we can increase memory capacity of > 1 TB per CPU, we also showcase performance improvement as we are seeing improved in bandwidth of 18-22%. Learn more by visiting www.micron.com/cxl.
- [Microchip: HP Memory Capacity & Bandwidth Expansion](https://computeexpresslink.org/resource/microchip-hp-memory-capacity-bandwidth-expansion/) - The SMC2000, CXL Smart Memory Controller, facilitates HPC applications by increasing the memory capacity available per core and memory bandwidth per core.
- [Lightelligence: Photowave: Optical CXL Interconnect for Composable Data Center Architectures](https://computeexpresslink.org/resource/lightelligence-photowave-optical-cxl-interconnect-for-composable-data-center-architectures/) - The demonstration showcases the benefits of CXL over optics connectivity for large language model (LLM) inference. The AI model is stored in two Micron CXL memory expansion modules which are optically connected by a pair of Photowave PCIe cards to an AMD Genoa CXL 1.1 server and NVIDIA A10 GPU. MemVerge’s memory machine software is
- [IntelliProp: Composable and Managed CXL Fabric Demo](https://computeexpresslink.org/resource/intelliprop-composable-and-managed-cxl-fabric-demo/) - IntelliProp’s CXL Extensible Memory Modules enables the composable data center transformation – fundamentally changing the performance, efficiency, and cost of data centers. Learn more by visiting https://intellipropipcores.com/.
- [AMD: Enhancing AI with CXL Memory Tiering](https://computeexpresslink.org/resource/amd-enhancing-ai-with-cxl-memory-tiering/)
- [Astera Labs: Demonstrating Breakthrough Memory Bandwidth and Performance for HPC and AI with Leo Memory Connectivity Platform](https://computeexpresslink.org/resource/astera-labs-demonstrating-breakthrough-memory-bandwidth-and-performance-for-hpc-and-ai-with-leo-memory-connectivity-platform/) - Astera Labs is demonstrating its Leo Smart Memory Controllers, the industry’s highest performant memory controller, enabling CXL-attached memory for memory-intensive AI and HPC workloads. Learn more: Leo Smart Memory Controllers Cloud-Scale Interop Lab for CXL Video: Leo Breaks Through the Memory Wall Video: Accelerating Database Performance with Leo
- [Cadence: Silicon-Proven Subsystem IP for CXL Host and Endpoint from Cadence Live Demo with Viavi Protocol Analyzer](https://computeexpresslink.org/resource/cadence-silicon-proven-subsystem-ip-for-cxl-host-and-endpoint-from-cadence-live-demo-with-viavi-protocol-analyzer/)
- [Introducing the CXL 4.0 Specification](https://computeexpresslink.org/resource/introducing-the-cxl-4-0-specification/)
- [Introducing Compute Express Link® (CXL®) 4.0: Significant Improvements in Bandwidth, Connectivity, Memory Maintenance, and Security](https://computeexpresslink.org/resource/introducing-compute-express-link-cxl-4-0-significant-improvements-in-bandwidth-connectivity-memory-maintenance-and-security/)
- [How CXL Transforms Server Memory Infrastructure](https://computeexpresslink.org/resource/how-cxl-transforms-server-memory-infrastructure/)
- [Advantages of CXL Memory Sharing for Emerging Applications](https://computeexpresslink.org/resource/advantages-of-cxl-memory-sharing-for-emerging-applications/)
- [An Overview of the CXL 3.X Specification](https://computeexpresslink.org/resource/an-overview-of-the-cxl-3-x-specification/)
- [Breaking Memory Barriers: CXL's Game-Changing Impact on AI/ML](https://computeexpresslink.org/resource/breaking-memory-barriers-cxls-game-changing-impact-on-ai-ml/)
- [Compute Express Link® 2.0 White Paper](https://computeexpresslink.org/resource/compute-express-link-2-0-white-paper/)
- [ABI Research - Opportunities and Challenges for Compute Express Link (CXL)](https://computeexpresslink.org/resource/abi-research-opportunities-and-challenges-for-compute-express-link-cxl/)
- [Making Memories at HyperScale with CXL®](https://computeexpresslink.org/resource/making-memories-at-hyperscale-with-cxl/)
- [An Overview of RAS for Compute Express Link® Covering from CXL® 2.0 to CXL® 3.1](https://computeexpresslink.org/resource/an-overview-of-ras-for-compute-express-link-covering-from-cxl-2-0-to-cxl-3-1/)
- [Exploring CXL® Use Cases and Implementations](https://computeexpresslink.org/resource/exploring-cxl-use-cases-and-implementations/)
- [Introducton to Compute Express Link® (CXL®) Technology](https://computeexpresslink.org/resource/introducton-to-compute-express-link-cxl-technology/)
- [Introduction to Compute Express Link®](https://computeexpresslink.org/resource/introduction-to-compute-express-link/)
- [Exploring Compute Express Link® (CXL®) Cache Coherency](https://computeexpresslink.org/resource/exploring-compute-express-link-cxl-cache-coherency/)
- [Introducing Compute Express Link® (CXL®) 3.0](https://computeexpresslink.org/resource/introducing-compute-express-link-cxl-3-0/)
- [An Introduction to Compute Express Link (CXL) Technology](https://computeexpresslink.org/resource/an-introduction-to-compute-express-link-cxl-technology/)
- [Introducing the CXL 3.1 Specification](https://computeexpresslink.org/resource/introducing-the-cxl-3-1-specification/)
- [Gen-Z Specification Archive](https://computeexpresslink.org/resource/gen-z-specification-archive/) - Click Below to Download from the Gen-Z Specification Archive: Gen-Z Core Specification 1.1e Must download via Causeway due to large file size. If you are not a CXL Member and looking to access this specification, please email CXL Administration (admin@computeexpresslink.org). Gen-Z PHY Specification 1.1 Gen-Z Fabric Management Specification 1.1
- [CCIX Specification Archive](https://computeexpresslink.org/resource/ccix-specification-archive/) - Click Below to Download from the CCIX Specification Archive: CCIX Base Specification 1.0 CCIX Base Specification Revision 1.0a Version 1.0 CCIX Base Specification Revision 1.1 Version 1.0 CCIX Base Specification Revision 2.0 Version 1.0
- [OpenCAPI Specification Archive](https://computeexpresslink.org/resource/opencapi-specification-archive/) - Click Below to Download from the OpenCAPI Consortium Specification Archive: 25 Gbps Physical Signaling Specification LPC (Memory Agent) Reference Design Guide OpenCAPI AFU Address Space Usage OpenCAPI 3.0 - 25 Gbps PHY Mechanical Specification OpenCAPI 3.0 - Transaction Layer Specification OpenCAPI 3.0 Ready Definition OpenCAPI 3.0 Certified Definition OpenCAPI Discovery and Configuration Architecture Specification OpenCAPI
- [Intel: CXL Memory Modes on Future Generation Intel Xeon CPUs](https://computeexpresslink.org/resource/intel-cxl-memory-modes-on-future-generation-intel-xeon-cpus/) - Demo 1: Database workload performance enhancement using CXL memory on Intel’s 5th gen Xeon (codename: Emerald Rapids) processor Demo 2: System memory TCO reduction using Flat Memory Mode on Intel’s next generation Xeon (codename: Granite Rapids) processor
- [CXL 2.0 Keynote](https://computeexpresslink.org/resource/cxl-2-0-keynote/)
- [Compute Express Link® Overview](https://computeexpresslink.org/resource/compute-express-link-overview-presentation/)
- [Compute Express Link® (CXL®): A Coherent Interface for Ultra-High-Speed Transfers](https://computeexpresslink.org/resource/compute-express-link-cxl-a-coherent-interface-for-ultra-high-speed-transfers/)
- [Exploring Coherent Memory and Innovative Use Cases [PowerPoint]](https://computeexpresslink.org/resource/exploring-coherent-memory-and-innovative-use-cases-powerpoint/)
- [Memory Challenges and CXL Solutions](https://computeexpresslink.org/resource/memory-challenges-and-cxl-solutions/)
- [Introducing the Compute Express Link® 2.0 Specification](https://computeexpresslink.org/resource/introducing-the-compute-express-link-2-0-specification-december-2020-presentation/)
- [Compute Express Link® 2.0 Specification: Memory Pooling](https://computeexpresslink.org/resource/compute-express-link-2-0-specification-memory-pooling/)
- [Compute Express Link® (CXL®): Supporting Persistent Memory](https://computeexpresslink.org/resource/compute-express-link-cxl-supporting-persistent-memory/)
- [Compute Express Link® (CXL®) Link-level Integrity and Data Encryption (CXL IDE)](https://computeexpresslink.org/resource/compute-express-link-cxl-link-level-integrity-and-data-encryption-cxl-ide/)
- [An Overview of the Compute Express Link® (CXL®) 2.0 ECN](https://computeexpresslink.org/resource/an-overview-of-the-compute-express-link-cxl-2-0-ecn-december-2021-presentation/)
- [Introduction to the Compute Express Link® (CXL®) Fabric Manager](https://computeexpresslink.org/resource/introduction-to-the-compute-express-link-cxl-fabric-manager/)
- [CXL 1.1 vs. CXL 2.0 – What’s the difference?](https://computeexpresslink.org/resource/cxl-1-1-vs-cxl-2-0-whats-the-difference-june-2022-presentation/)
- [CXL 3.0: Enabling composable systems with expanded fabric capabilities](https://computeexpresslink.org/resource/cxl-3-0-enabling-composable-systems-with-expanded-fabric-capabilities/)
- [A look into the CXL device ecosystem and the evolution of CXL use cases](https://computeexpresslink.org/resource/a-look-into-the-cxl-device-ecosystem-and-the-evolution-of-cxl-use-cases/)
- [Compute Express LinkTM (CXL®): An Open Industry Standard for Composable Computing [FMS 2023 Tutorial ]](https://computeexpresslink.org/resource/compute-express-linktm-cxl-an-open-industry-standard-for-composable-computing-fms-2023-tutorial/)
- [Compute Express Link® (CXL ®) Device Ecosystem and Usage Models [FMS 2023]](https://computeexpresslink.org/resource/compute-express-link-cxl-device-ecosystem-and-usage-models-fms-2023-presentation/)
- [An Overview of Reliability, Availability, and Serviceability (RAS) in Compute Express Link® 2.0](https://computeexpresslink.org/resource/an-overview-of-reliability-availability-and-serviceability-ras-in-compute-express-link-2-0-february-2021-white-paper/)
- [CXL 3.0 specification](https://computeexpresslink.org/resource/cxl-3-0-specification-august-2022-white-paper/)
- [CXL Consortium Compliance Program Overview: Integrators List & Feature Testing](https://computeexpresslink.org/resource/cxl-consortium-compliance-program-overview-integrators-list-feature-testing/)
- [Introducing Compute Express Link® (CXL®) 3.1: Significant Improvements in Fabric Connectivity, Memory RAS, Security and more!](https://computeexpresslink.org/resource/introducing-compute-express-link-cxl-3-1-significant-improvements-in-fabric-connectivity-memory-ras-security-and-more/)

## Categories

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## Categories

- [Press Releases](https://computeexpresslink.org/cxl-category/press-releases/)
- [Members in the News](https://computeexpresslink.org/cxl-category/members-in-the-news/)
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- [Member Press Releases](https://computeexpresslink.org/cxl-category/member-press-releases/)
- [Webinar](https://computeexpresslink.org/cxl-category/webinar/)

## Member Levels

- [Board of Directors](https://computeexpresslink.org/member-level/board-of-directors/)
- [Contributors](https://computeexpresslink.org/member-level/contributors/)
- [Adopters](https://computeexpresslink.org/member-level/adopters/)

## Resource Types

- [White Papers](https://computeexpresslink.org/resource-type/white-papers/)
- [Presentations](https://computeexpresslink.org/resource-type/presentations/)
- [Demos](https://computeexpresslink.org/resource-type/demo/)
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- [CCIX Specification Archive](https://computeexpresslink.org/resource-type/ccix-specifications/)
- [OpenCAPI Specification Archive](https://computeexpresslink.org/resource-type/opencapi-specification/)
- [Gen-Z Specification Archive](https://computeexpresslink.org/resource-type/gen-z-specification-archive/)

## Roles

- [Officers](https://computeexpresslink.org/leader-role/officers/)
- [Board of Directors](https://computeexpresslink.org/leader-role/board-of-directors/)